Controller that supports data merging utilizing a slice addressable memory array
First Claim
1. A method of merging first and second data sets from different sources in a slice addressable random-access memory array including an associated array of slice enable bits, said method comprising the steps of:
- enabling a row of the slice addressable random access memory array for writing;
designating a slice of said row of the slice-addressable random access memory array enabled for writing by setting an associated bit in the associated array of slice enable bits;
writing the first data set to the designated slice of said row of the slice addressable random access memory enabled for writing; and
writing the second data set to previously undesignated slices of said row of the slice addressable random access memory enabled for writing.
1 Assignment
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Accused Products
Abstract
A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.
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Citations
24 Claims
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1. A method of merging first and second data sets from different sources in a slice addressable random-access memory array including an associated array of slice enable bits, said method comprising the steps of:
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enabling a row of the slice addressable random access memory array for writing; designating a slice of said row of the slice-addressable random access memory array enabled for writing by setting an associated bit in the associated array of slice enable bits; writing the first data set to the designated slice of said row of the slice addressable random access memory enabled for writing; and writing the second data set to previously undesignated slices of said row of the slice addressable random access memory enabled for writing. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory write operation, said computer system including a slice addressable random access memory buffer comprised of at least one word line corresponding to a cache line, and an array of slice enable bits associated with slices of the word line of the slice addressable random access memory buffer, said method comprising the steps of:
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setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to the slices of said word line associated with said set slice enable bits in said slice addressable random access memory buffer; and write merging data from the modified cache line to the slices of said word line not associated with said set slice enable bits in said slice addressable random access memory buffer.
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9. A data buffer in a memory controller of a computer system including a processor, a processor bus, and a memory subsystem, said data buffer comprising:
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a slice addressable random access memory array having a plurality of word lines comprised of slices; a memory bus configured for communication between said slice addressable random access memory array and said memory subsystem; a first interface coupled between said slice addressable random access memory array and said processor bus, said first interface including a plurality of individually enabled-data paths configured for data communication with said slices of said slice addressable random access memory array and a second interface coupled between said slice addressable random access memory array and an input/output bus said second interface including a plurality of individually enabled data paths configured for data communication with said slices of said slice addressable random access memory array. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer system, comprising:
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a host memory; a plurality of agents; a memory controller operatively connected to said plurality of agents, via a system bus and/or an input/output bus, operatively connected to said host memory, via a memory bus, and configured to perform data merging to preserve cache coherency, said memory controller comprising; a slice addressable random access memory array having multiple input/output ports and a plurality of word lines comprised of slices; a first interface provided to interface said slice addressable random access memory array with said system bus for data communication with said slices of said slice addressable random access memory array; and a second interface provided to interface said slice addressable random access memory array with said input/output bus for data communication with said slices of said slice addressable random access memory array. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification