System and method for executing and completing store instructions

• US 6,134,646 A
• Filed: 07/29/1999
• Issued: 10/17/2000
• Est. Priority Date: 07/29/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Feiste, Kurt Alan, Ngo, Tai Dinh, Tuvell, Amy May
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/364,012
• Time in Patent Office: 446 Days
• Field of Search: 712/23, 712/24, 712/41, 712/216
• US Class Current: 712/23
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.

Claims

1. A method for executing a store instruction in a processor, comprising the steps of:

executing address generation portion of the store instruction in a load/store unit;

executing write data portion of the store instruction in an execution unit other than the load/store unit; and

completing the store instruction when all instructions older than the store instruction have completed and when all instructions in an instruction group that included the store instruction have finished.

2. The method as recited in claim 1, wherein the execution unit other than the load/store unit is the floating point unit if the store instruction is a floating point store instruction.

3. The method as recited in claim 1, wherein the execution unit other than the load/store unit is the fixed point unit if the store instruction is a fixed point store instruction.

4. The method as recited in claim 3, wherein the fixed point store instruction is cracked into two internal op codes.

5. The method as recited in claim 4, wherein a first one of the two internal op codes is a store address generation internal op code executed by the load/store unit, and wherein a second one of the two internal op codes is a store data internal op code executed by the fixed point unit.

6. The method as recited in claim 1, further comprising the steps of:

writing an address generated by the address generation portion of the store instruction into a store reorder queue; and

writing the data generated by the write data portion of the store instruction into a store data queue.

7. The method as recited in claim 6, further comprising the steps of:

marking in store reorder queue the store instruction as ready for execution;

determining if an oldest entry in the store reorder queue is ready for execution; and

writing the data from the store data queue to a cache using the address.

8. A processor comprising:

a load/store unit for executing an address generation portion of a store instruction;

an execution unit other than the load/store unit for executing a store data portion of the store instruction; and

circuitry for completing the store instruction when all instructions older than the store instruction have completed and when all instructions in an instruction group that included the store instruction have finished.

9. The processor as recited in claim 8, wherein the execution unit other than the load/store unit is the floating point unit if the store instruction is a floating point store instruction.

10. The processor as recited in claim 8, wherein the execution unit other than the load/store unit is the fixed point unit if the store instruction is a fixed point store instruction.

11. The processor as recited in claim 10, further comprising an instruction dispatch unit for cracking the fixed point store instruction into two internal op codes.

12. The processor as recited in claim 11, wherein a first one of the two internal op codes is a store address generation internal op code executed by the load/store unit, and wherein a second one of the two internal op codes is a store data internal op code executed by the fixed point unit.

13. The processor as recited in claim 8, wherein the load/store unit writes an address generated by the address generation portion of the store instruction into a store reorder queue, and wherein the execution unit writes the data generated by the write data portion of the store instruction into a store data queue.

14. The processor as recited in claim 13, further comprising:

circuitry for marking in the store reorder queue the store instruction as ready to be written to a cache;

circuitry for determining if an oldest entry in the store reorder queue is ready for execution; and

circuitry for writing the data from the store data queue to the cache using the address.

15. The processor as recited in claim 9, wherein the floating point store instruction is treated as two different internal operations after dispatch.

16. A processor comprising:

an instruction cache receiving an instruction;

circuitry for determining if the instruction is a store instruction;

circuitry for determining if the store instruction is a floating point store instruction or a fixed point store instruction when the instruction is a store instruction;

a load/store unit;

a fixed point unit;

a floating point unit;

an instruction dispatch unit for marking the store instruction to be sent to the load/store unit and the floating point unit when the store instruction is a floating point store instruction, wherein the instruction dispatch unit cracks the store instruction into a store address generation internal op code and a store data internal op code when the store instruction is a fixed point store instruction, wherein the store address generation internal op code is marked to be sent to the load/store unit, and wherein the store data internal op code is marked to be sent to the fixed point unit;

circuitry for dispatching the floating point store instruction to an issue queue in each of the load/store unit and the floating point unit;

circuitry for dispatching the store address generation internal op code to the issue queue in the load/store unit;

circuitry for dispatching the store data internal op code to an issue queue in the fixed point unit;

circuitry for executing the floating point store instruction in the load/store unit when the load/store unit is ready;

circuitry for executing the floating point store instruction in the floating point unit when the floating point unit is ready;

circuitry for executing the store address generation internal op code in the load/store unit when the load/store unit is ready;

circuitry for executing the store data internal op code in the fixed point unit when the fixed point unit is ready;

circuitry for writing an address generated in the load/store unit into a store reorder queue in the load/store unit;

circuitry for writing write data into a store data queue;

circuitry for determining if all instructions older than the store instruction have completed;

circuitry for determining if all instructions in a group that included the store instruction have finished when all instructions older than the store instruction have completed;

circuitry for completing the store instruction when all instructions in the group that included the store instruction have finished;

circuitry for marking in the store reorder queue the store instruction as ready for execution;

circuitry for determining if an oldest entry in the store reorder queue is ready for execution; and

circuitry for storing the store data into a cache using the address generated.