Method and apparatus for testing memory devices and displaying results of such tests

• US 6,134,677 A
• Filed: 08/20/1997
• Issued: 10/17/2000
• Est. Priority Date: 12/04/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lindsay, Brent
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elisca, Pierre E.
• Application Number:
  US08/915,074
• Time in Patent Office: 1,154 Days
• Field of Search: 714/42, 714/48, 714/57, 714/53, 714/46, 714/54
• US Class Current: 714/42
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested.

Claims

1. In a testing system having a processor and an output device, an apparatus for identifying errors in a semiconductor device, wherein the semiconductor device has a plurality of circuit locations addressable by logical addresses, the apparatus comprising:

an error memory for storing error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, wherein the error memory is addressable by physical addresses; and

a programmable router circuit coupled to the error memory and the semiconductor device, wherein the programmable router circuit converts the logical addresses to physical addresses and causes the error data from the plurality of circuit locations in the semiconductor device to be routed to selected locations in the error memory, wherein the error memory provides error data corresponding to selected physical addresses to the processor in response to spatial addresses from the processor, and wherein the error data corresponds to the spatial addresses capable of being visually output by the output device.

2. The apparatus of claim 1 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the processor based on a layout of the circuit locations in the semiconductor device.

3. The apparatus of claim 1 wherein the programmable router circuit is a field programmable gate array.

4. The apparatus of claim 1, further comprising a programmable circuit programmable by the processor based on a layout of memory locations in the error memory.

5. The apparatus of claim 1 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.

6. The apparatus of claim 1, further comprising a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.

7. A testing apparatus for testing a semiconductor device formed on a substrate, the semiconductor device having a plurality of circuits addressable by logical addresses, the apparatus comprising:

a processor and display device capable of providing test data to and from the plurality of circuits in the semiconductor device based on the logical addresses;

a comparator circuit coupled to the semiconductor device for comparing the test data provided to the plurality of circuits to the data from the plurality of circuits and producing error data in response to such comparison, and wherein the processor and display device is capable of displaying the error data at spatial addresses; and

a mapping circuit having

an error memory for storing the error data, wherein the error memory is addressable by physical addresses,

a programmable router circuit coupled to the processor, the comparator circuit, and the error memory, wherein the programmable router circuit converts the logical addresses to physical addresses and causes the error data to be routed to selected locations in the error memory, and wherein the error memory provides error data corresponding to physical addresses for display by the processor and display device.

8. The testing apparatus of claim 7, further comprising:

a test bed for releasably securing the substrate; and

a plurality of test probes for electrically intercoupling between the semiconductor device and the processor.

9. The testing apparatus of claim 7, further comprising a magnifying optical inspection device positioned over the substrate for allowing optical inspection of an upper surface of the substrate.

10. The apparatus of claim 7 wherein the programmable router circuit is a field programmable gate array.

11. The apparatus of claim 7 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the processor and display device based on a layout of the circuits in the semiconductor device.

12. The apparatus of claim 7, further comprising a field programmable gate array, programmable by the processor and display device based on a layout of the memory locations in the error memory.

13. The apparatus of claim 7 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.

14. The apparatus of claim 7, further comprising a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.

15. A method of testing a semiconductor device and outputting locations of errors in the semiconductor device, the semiconductor device having a plurality of locations addressable by logical address signals, the method comprising the steps of:

programming a router for converting the logical addresses of the semiconductor device to physical addresses based on a layout of the locations in the semiconductor device;

programming a converter for converting spatial addresses to physical addresses based on a layout of a plurality of memory locations in an error memory;

applying test signals to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error memory based on the programmed router; and

reading the error data from the error memory and visually outputting the error data at spatial locations based on the programmed converter.

16. The method of claim 15, further comprising the steps of:

determining a pattern for the logical address signals for the locations in the semiconductor device, and

determining an optimal routing routine for converting the logical addresses of the semiconductor device to physical addresses based on the pattern for the logical address signals of the locations in the semiconductor device.

17. The method of claim 15, further comprising the steps of:

determining a pattern for addresses of the memory locations in the error memory, and

determining an optimal mapping routine for mapping the spatial addresses to physical addresses based on the pattern for the addresses of the memory locations in the error memory.

18. The method of claim 15 wherein the step of programming a router includes loading a routine into a field programmable gate array.

19. The method of claim 15 wherein the step of programming a converter includes loading a routine into a field programmable gate array.

20. The method of claim 15 wherein the step of programming a router includes loading a routine into a read only memory that stores a look-up table for converting the logical addresses to physical addresses.

21. The method of claim 15 wherein the step of programming a converter includes loading a routine into a read only memory that stores a look-up table for converting spatial addresses to physical addresses.

22. A testing system for testing a semiconductor memory device, the testing system having a computer and a display device, and the memory device being addressable by logical addresses, the system comprising:

an error catch memory for storing error data corresponding to a comparison between written and read data to and from the memory device, each memory cell of the catch memory being addressable by a physical address;

a programmable router circuit coupled to the catch memory and the memory device, for converting the logical addresses to physical addresses, and routing for storage of the error data from the locations within the memory device to selected memory cells within the catch memory; and

a programmable topological circuit coupled to the catch memory and computer, the topological circuit receiving spatial addresses from the computer, converting the spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to allow the error data from the memory device to map to spatial addresses on the display device for displaying the locations of errors in the memory device.

23. A method comprising the steps of:

loading a routing routine, based on a layout of memory locations in a memory device, which converts logical addresses of the memory device to physical addresses;

loading a mapping routine, based upon a layout of a plurality of memory cells within an error catch memory, into a topological circuit for converting spatial addresses to physical addresses;

continually applying a test pattern to the memory device, determining error data from the memory device and routing it to the catch memory based on the routing routine; and

substantially simultaneously with the step of applying a test pattern, constantly reading the error data from the catch memory and displaying the error data at spatial locations on a display device based upon the mapping routine.