Semiconductor memory device with spare memory cell

• US 6,134,681 A
• Filed: 01/08/1998
• Issued: 10/17/2000
• Est. Priority Date: 06/19/1997
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mori, Shigeru, Akamatsu, Hiroshi
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/004,299
• Time in Patent Office: 1,013 Days
• Field of Search: 714/7, 714/54, 714/710, 714/711, 365/200, 365/201
• US Class Current: 714/710
• CPC Class Codes: G11C 29/84 with improved access time or stability
• CPC Class Codes: G11C 29/842 by introducing a delay in a signal path

Abstract

In an SDRAM, when a spare column selection line is not used, access to a column selection line is started at a first time at which complementary column address signals are defined, and access to the column selection line is stopped until a second time at which the level of a redundant column decoder activation signal is defined when the spare column selection line is used. Compared with the case in which access to the column selection line is always stopped until the second time, the access speed is increased.

Claims

1. A semiconductor memory device in which data is electrically rewritable, comprising:

a plurality of memory cells to which addresses signals specific thereto are allocated respectively;

a selection line provided corresponding to each memory cell for selecting a corresponding memory cell;

a spare memory cell for replacing a defective one of said plurality of memory cells;

a spare selection line for selecting said spare memory cell;

a first decoder which outputs, in response to input of an address signal designating said defective memory cell, a first activation signal after a first time has passed from the time of the input;

a second decoder which is associated with each selection line, and starts, in response to input of an address signal designating a memory cell associated with the selection line, output of a second activation signal after a second time shorter than said first time has passed from the time of the input and stops, in response to the output of said first activation signal from said first decoder, the output of said second activation signal;

a signal generation circuit outputting a third activation signal after said first time has passed from the time of the input of said address signal if said defective memory cell is present and outputting said third activation signal after said second time has passed from the time of the input of said address signal if said defective memory cell is absent;

a first selection circuit responding to the output of said first activation signal from said first decoder and the output of said third activation signal from said signal generation circuit to set said spare selection line at selection level and select said spare memory cell;

a second selection circuit associated with each second decoder and responding to the output of said second activation signal from the associated second decoder and the output of said third activation signal from said signal generation circuit to set an associated selection line at selection level and select an associated memory cell; and

a write/read circuit writing/reading data into/from said spare memory cell selected by said first selection circuit and the memory cell selected by said second selection circuit.

2. The semiconductor memory device according to claim 1, wherein said signal generation circuit includes:

a first delay circuit for delaying a reference signal which is in synchronization with said address signal by said first time to output the reference signal;

a second delay circuit for delaying said reference signal by said second time to output the reference signal;

a fuse used for programming whether or not said defective memory cell is present;

a gate circuit which passes an output signal from said first delay circuit as said third activation signal if said fuse programs presence of said defective memory cell and passes an output signal from said second delay circuit as said third activation signal if said fuse programs absence of said defective memory cell.

3. The semiconductor memory device according to claim 1, wherein said signal generation circuit includes

a plurality of delay circuits connected in series for delaying a reference signal which is in synchronization with said address signal by said first or second time to generate said third activation signal, and each delay circuit includes:

a first transistor of a first conductivity type having its input electrode connected to an input node and having its first electrode connected to an output node;

a second transistor of a second conductivity type having its input electrode connected to said input node and having its first electrode connected to said output node;

a first fuse connected between a line of supply potential and a second electrode of said first transistor, blown off if said defective memory cell is present;

a second fuse connected between a line of ground potential and a second electrode of said second transistor, blown off if said defective memory cell is present; and

first and second resistance elements connected in parallel with said first and second fuses respectively.

4. The semiconductor memory device according to claim 1, wherein

said signal generation circuit includes a plurality of delay circuits connected in series for delaying a reference signal which is in synchronization with said address signal by said first or second time to generate said activation signal, and each delay circuit includes;

first and second transistors of a first conductivity type connected in series between the line of supply potential and an output node, each having its input electrode connected to an input node;

third and fourth transistors of a second conductivity type connected in series between the line of ground potential and said output node, each having its input electrode connected to said input node; and

first and second fuses connected in parallel with said first and fourth transistors respectively, blown off if said defective memory cell is present.