Semiconductor device and method of fabricating the same

• US 6,137,135 A
• Filed: 08/07/1998
• Issued: 10/24/2000
• Est. Priority Date: 08/08/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Saito, Hiroaki, Kubo, Hirotoshi, Kitagawa, Masanao, Kuwako, Eiichiroh
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US09/131,345
• Time in Patent Office: 809 Days
• Field of Search: 257/329, 257/328, 257/341, 438/212
• US Class Current: 257/328
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of "γ" which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.

Claims

1. A semiconductor device comprising:

a trench formed in a semiconductor layer;

a gate oxide layer formed on an inner wall of said trench;

a gate conductor material embedded in said trench covered with the gate oxide layer; and

a channel region formed in a boundary of said semiconductor layer with said gate oxide layer,

wherein the inner wall of the trench extending from the bottom of said trench to the surface of the semiconductor layer has a curve, and an angle of a tangent line of said curve with respect to the surface of said semiconductor layer decreases constantly from the vicinity of a lower end of said channel region toward the surface of said semiconductor layer.

2. The semiconductor device as claimed in claim 1,

wherein said semiconductor layer is a first semiconductor layer of a first conduction type and

said semiconductor device further comprises:

a source region of an opposite conduction type formed on a surface of said first semiconductor layer;

a drain region of a second semiconductor layer of an opposite conduction type formed on a rear surface of said first semiconductor layer.

3. A semiconductor device comprising a semiconductor substrate including a first layer having a first conduction type and serving as a drain region, a second layer formed on said first layer and having the first conduction type more lightly doped than the first layer, and a third layer formed on the second layer, having a second conduction type opposite to the first conduction type and serving as a channel region;

a trench formed in a grid pattern which extends from said third layer located on a surface of said semiconductor substrate to said second layer;

a conductive material serving as a gate embedded in said trench covered with an insulating layer formed on an inner surface of said trench; and

a source region having the first conduction type formed in the surface of said third layer corresponding to a region surrounded by an opening of said trench, wherein the inner wall of the trench extending from a bottom of said trench to the surface of the semiconductor layer has a curve, and an angle of a tangent line of said curve with respect to the surface of said semiconductor layer decreases constantly from the vicinity of a lower end of said channel region toward the surface of said semiconductor layer.

4. The semiconductor device as claimed in claim 3, wherein an area of the trench, when the trench is cut horizontally, has an increasing rate from the lower end of said channel region toward the surface of the semiconductor layer and a substantially zero increasing rate in the vertical vicinity of the lower end of the channel region.

5. The semiconductor device as claimed in claim 3, wherein assuming that a vertical section of said trench has a length OP of an opening, a depth D₁, a width BT₂ of a bottom and a length D₁ of a sloping line connecting the edge of the opening to that of the bottom, 2×

D₂ +BT₂ <

2×

D₁ +OP.

6. The semiconductor device as claimed in claim 4, wherein a bottom of said trench overlaps the vicinity of the surface of said second layer.

7. A vertical type MOS semiconductor device having a trench formed in a semiconductor layer and embedded with a gate conductor material in the trench, the inner surface of which is covered with an oxide layer, wherein said trench has a sectional shape having a dimension relationship:

D₂ <

D₁ +(OP-BT₂)/2where OP;

a length of an opening of the trench,

D₁ ;

a depth of the trench,

D₂ ;

a length of a curve connecting the top of the opening to a bottom of the trench,

BT₂ ;

a length of the bottom.

8. A vertical type MOS semiconductor device comprising:

a trench formed in a semiconductor layer;

a gate oxide layer formed on an inner surface of said trench;

a gate material embedded in the trench, the inner surface of which is covered with said gate oxide layer; and

a source region (or drain region) formed on the periphery of an opening of said trench and a drain region (or source region) formed in the vicinity of a bottom of said trench,

wherein said trench has a curve which is convex toward above from a line connecting point S, which is a crossing point of the bottom of said source region (or drain region) and said trench, to point d, which is a lower end of a channel formed at a boundary between said gate insulating layer and said semiconductor layer, and is substantially vertical in the semiconductor layer, and is substantially vertical in the vicinity of the lower end of the channel region.

9. The vertical type MOS semiconductor device as claimed in claim 8, wherein the bottom of said trench has a prescribed width.

10. The vertical type MOS semiconductor device as claimed in claim 9, wherein said MOS semiconductor device is a power MOS transistor.

11. The vertical type MOS semiconductor device as claimed in claim 9, wherein said MOS semiconductor device is an IGBT.