Planarized deep-shallow trench isolation for CMOS/bipolar devices

• US 6,137,152 A
• Filed: 04/22/1998
• Issued: 10/24/2000
• Est. Priority Date: 04/22/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wu, Shye-Lin
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/064,976
• Time in Patent Office: 916 Days
• Field of Search: 257/506, 257/510, 257/513, 438/424, 438/426, 438/427, 438/430, 438/431, 438/432, 438/433
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.

Claims

1. A trench isolation before planarization formed on a substrate, said trench isolation comprising:

a nitride layer formed on said substrate;

a first trench with a first opening having a first width formed in said substrate and said nitride layer;

a second trench with a second opening having a second width formed in the bottom of said first trench and extending into said substrate, wherein said second width is narrower than said first width, a depth of said second trench is deeper than that of said first trench;

a first oxide layer for relieving a stress lying on the surface of said second trench, on the lower part of said first trench and between the interface of said substrate and said nitride layer;

an oxynitride layer acting as an oxidation buffer to improve the isolation formed along the upper surface of said nitride layer, the surface of said first trench and along the surface of said first oxide layer formed on the surface of said second trench;

a polysilicon plug refilled in said second trench;

a second oxide layer refilled into said first trench and on the upper surface of said oxynitride layer that lying on said nitride layer; and

a filling layer formed on said second oxide layer for said planarization.

2. The trench isolation of claim 1, wherein said filling layer comprises BPSG.

3. The trench isolation of claim 1, wherein said filling layer comprises SOG.