Hybrid package including a power MOSFET die and a control and protection circuit die with a smaller sense MOSFET

• US 6,137,165 A
• Filed: 06/25/1999
• Issued: 10/24/2000
• Est. Priority Date: 06/25/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thierry, Vincent
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/344,704
• Time in Patent Office: 487 Days
• Field of Search: 257/690, 257/691, 257/723, 257/730, 257/666, 257/676, 257/725, 257/724, 257/728, 257/902, 257/734, 257/203, 257/204, 257/207, 257/355, 257/356, 257/226, 257/426, 257/444 , 257/500
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49051 Connectors having different shapes
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12035 : Zener diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H03K 17/0822 : in field-effect transistor switches
• CPC Class Codes: H03K 2017/0806 : against excessive temperature

Abstract

A power MOSFET die and a logic and protection circuit die are mounted on a common lead frame pad, such as a TO220 lead frame pad. The logic and protection circuit die includes a MOSFET that is connected in parallel with the power MOSFET but which is smaller than the power MOSFET and which dissipates power at a predetermined fraction of that of the power MOSFET. The logic and protection circuit die also includes a temperature sensor that is in close proximity to the MOSFET and determines the temperature of the MOSFET. The die also includes another temperature sensor that is located distant from the MOSFET to determine the temperature of the lead frame. The temperature of the power MOSFET can be determined from the temperature measured by these two sensors and from the ratio of the power dissipated by the two MOSFETs.

Claims

1. A semiconductor device contained in a package which includes a conductive lead frame having a main pad area and;

an insulation resin enclosure;

said semiconductor device comprising;

a first semiconductor die having opposing surfaces which contain respective electrodes and comprising a first semiconductor device;

a second semiconductor die having opposing surfaces at least one of which contains at least one electrode, and containing in one portion thereof a second semiconductor device having a thermal response corresponding to that of said first semiconductor device,

a first thermal sensor arranged on said second die at a position adjacent to said second semiconductor device,

a second thermal sensor arranged on said second die at a position more distant from said second semiconductor device then said first thermal sensor;

one of said opposing surfaces of each of said first and second semiconductor die being disposed atop and in thermal contact with said main pad area and being laterally spaced from one another, at least said one opposing surface of said first semiconductor die being in electrical contact with said main pad area;

the opposite ones of said opposing surfaces of said first and second die being electrically connected to each other such that said first and second semiconductor devices are connected in parallel.

2. The device of claim 1, wherein said semiconductor die are MOS gated semiconductor devices.

3. The device of claim 1 wherein said first semiconductor die is a first MOSFET having a source electrode and a gate electrode disposed in said opposite one of said opposing surfaces, and wherein the surface of said first die that is in contact with said main pad area is a drain electrode.

4. The device of claim 3 wherein said second semiconductor die is a second MOSFET having a source electrode, a drain electrode and a gate electrode;

at least said source and said gate electrodes being disposed in said opposite one of said opposing surfaces;

said source electrode of said second MOSFET being connected to said source electrode of said first MOSFET and said gate electrode of said second MOSFET being connected to said gate electrode of said first MOSFET.

5. The device of claim 1 wherein said package is a TO220 device package.

6. The device of claim 1 wherein said first and second thermal sensors are each comprised of at least one polysilicon diode.

7. The device of claim 1 wherein said first and second thermal sensors are each comprised of a respective plurality of series connected polysilicon diodes.

8. The device of claim 1 wherein said first thermal sensor is disposed in a trench formed within said second die.

9. The device of claim 1 wherein said first thermal sensor senses the temperature of said second die.

10. The device of claim 1 wherein said second thermal sensor senses the temperature of said main pad area.

11. The device of claim 1 wherein said second semiconductor die includes an input terminal.

12. The device of claim 11 wherein said second semiconductor die includes a driver circuit for turning on and off said first and second semiconductor die as a function of an input signal supplied to said input terminal.

13. The device of claim 12 wherein said second semiconductor die further comprises a logic circuit for determining the temperature of said first semiconductor device from first and second temperature values measured by said first and second thermal sensors, respectively, and for supplying a control signal to said driver circuit as a function of the determined temperature of said first semiconductor die.

14. The device of claim 1 wherein the power dissipated by said second semiconductor device is less than that of said first semiconductor device.

15. A semiconductor device comprising:

a conductive lead frame having a main pad area and a plurality of pins that are separated from one another, said main pad area being electrically coupled to at least one of said plurality of pins;

a first semiconductor die having opposing surfaces which contain respective electrodes and containing a first semiconductor device;

a second semiconductor die having opposing surfaces at least one of which contains at least one electrode and comprising a second semiconductor device having a thermal response corresponding to that of said first semiconductor device, a first thermal sensor arranged on said second die at least adjacent to said second semiconductor device, and a second thermal sensor arranged on said second die distant from said second semiconductor device;

one of said opposing surfaces of each of said first and second semiconductor die being disposed atop and in thermal contact with said main pad area and being laterally spaced from one another, at least said one opposing surface of said first semiconductor die being in electrical contact with said main pad area;

the opposite ones of said opposing surfaces of said first and second die being electrically connected to respective ones of said pins and to each other such that said first and second semiconductor devices are connected in parallel; and

a molded housing for encapsulating said lead frame and said first and second die and said bonding wires;

said pins extending beyond an external boundary of said molded housing and available for external connection.

16. The device of claim 15, wherein said semiconductor die at least include respective MOS gated semiconductor devices.

17. The device of claim 15 wherein said first MOS gated semiconductor device is a first MOSFET having a source electrode and a gate electrode disposed in said opposite one of said opposing surfaces, and wherein the surface of said first die is in contact with said main pad area is said drain electrode;

said source electrode of said first MOSFET being connected to a respective one of said pins.

18. The device of claim 17 wherein said second MOS gated semiconductor device includes a second MOSFET having a source electrode, a drain electrode and a gate electrode;

at least said source and said gate electrodes being disposed in said opposite one of said opposing surfaces;

said source electrode of said second MOSFET being connected to said source electrode of said first MOSFET and said gate electrode of said second MOSFET being connected to said gate electrode of said first MOSFET.

19. The device of claim 15 wherein said plurality of pins includes at least one first pin that is integral with and extends from an edge of said main pad area, and at least two second pins that are separated from said main pad area.

20. The device of claim 19 wherein said second pins are disposed along said edge of said main pad area that contains said first pin.

21. The device of claim 20 wherein said said molded housing comprises a TO220 device package.

22. The device of claim 19 wherein at least one of said second pins is electrically connected to said first semiconductor die and another of said second pins is electrically connected to said second semiconductor die.

23. The device of claim 19 wherein said second semiconductor die includes an input terminal that is electrically connected to a respective one of said pins.

24. The device of claim 23 wherein said second semiconductor die includes a driver circuit for turning on and off said first and second semiconductor die as a function of an input signal supplied to said input terminal.

25. The device of claim 24 wherein said second semiconductor die further comprises a logic circuit for determining the temperature of said first semiconductor die from first and second temperature values measured by said first and second thermal sensors, respectively, and for supplying a control signal to said driver circuit as a function of the determined temperature of said first semiconductor die.

26. A integrated circuit device formed in a semiconductor die having opposing surfaces at least one of which contains at least one electrode, said integrated circuit device comprising:

an MOS gated semiconductor device;

a first thermal sensor arranged on said semiconductor die adjacent to said MOS gated semiconductor device for sensing the temperature of said MOS gated semiconductor device; and

a second thermal sensor arranged on said semiconductor die distant from said MOS gated semiconductor device for sensing the temperature of a substrate on which said semiconductor die is mounted.

27. The device of claim 26 wherein said MOS gated semiconductor device is a MOSFET having a source electrode, a drain electrode and a gate electrode;

at least said source electrode and said gate electrode of said MOSFET being formed in one of said opposing surfaces of said semiconductor die.

28. The device of claim 26 wherein said first and second thermal sensors are each comprised of at least one polysilicon diode.

29. The device of claim 26 wherein first and second thermal sensors are each comprised of a respective plurality of series connected polysilicon diodes.

30. The device of claim 26 wherein said first thermal sensor is disposed in a trench formed within said MOS gated semiconductor device.

31. The device of claim 26 wherein said one surface of said semiconductor die includes an input terminal.

32. The device of claim 31 wherein said semiconductor die includes a driver circuit for turning on and off at least said MOS gated semiconductor device as a function of an input signal supplied to said input terminal.

33. The device of claim 32 further comprising a logic circuit for determining the temperature of a remotely positioned second MOS gated semiconductor device from first and second temperature values measured by said first and second thermal sensors, respectively, and for supplying a control signal to said driver circuit as a function of the determined temperature of said further MOS gated semiconductor device;

said MOS gated device and said remotely positioned second MOS gated semiconductor device being mounted on a common thermally conductive substrate.