Switching DC-to-DC converter and conversion method with current sharing between paralleled channels

• US 6,137,274 A
• Filed: 02/02/2000
• Issued: 10/24/2000
• Est. Priority Date: 02/02/2000
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Rajagopalan, Jayendar
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/496,570
• Time in Patent Office: 265 Days
• Field of Search: 323/265, 323/271, 323/272, 323/282, 323/312, 323/315, 363/65
• US Class Current: 323/272
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02J 1/106 for load balancing, symmetrisation, or sharing

Abstract

A DC-to-DC converter having multiple power delivery channels, and including a current-sharing switching controller implemented as an integrated circuit, multi-channel circuitry (including parallel channels connected to one output node) external to the controller chip, and current sharing circuitry (including circuitry external to the controller chip and circuitry including current mirrors internal to the controller chip), and methods for generating PWM power switch control signals for use in (and performing DC-to-DC conversion using) such a DC-to-DC converter. Preferably, the current sharing circuitry generates individual channel current signals from voltage analogs thereof produced external to the controller chip, and superposes the individual channel current signals to produce an average current signal. Channel current error signals are generated by subtracting the individual channel current signals from the average current signal. The power switch control signal for each channel is generated in response to the channel current error signal for the appropriate channel and a feedback signal (an output voltage error signal) indicative of the output potential of the DC-to-DC converter relative to a reference potential, so that the DC-to-DC converter achieves a desired output potential with increased current sharing among the channels. The invention implements current sharing between channels of a DC-to-DC converter using simple circuitry external to the controller chip (and without an external bus which connects one channel to the other), and with simple, silicon-area efficient circuitry internal to the controller chip. Preferably, current mirror circuitry in the controller chip generates a set of identical average current signals, each of which is proportional to the average of the currents drawn from the individual channels, and additional current mirror circuitry generates a set of identical error current signals, each of which is an error current proportional to the difference between the DC-to-DC converter'"'"'s output potential and a reference potential.

Claims

1. A DC-to-DC converter having an input node for receiving an input potential, and an output node at which the converter asserts an output potential, wherein when a load is coupled to the output node, the load draws an output current from said output node, wherein the converter comprises:

current sharing circuitry;

a switching controller configured to generate at least two pulse width modulated power switch control signals, and having at least one reference input coupled to receive at least one signal indicative of a reference potential;

multiple power delivery channels connected in parallel between the input node and the output node, each of the power delivery channels including a power switch coupled to the controller for receiving a different one of the pulse width modulated power switch control signals; and

feedback circuitry, coupled between the output node and a feedback input of the controller, and configured to assert to the feedback input a feedback signal indicative of the output potential,

wherein the current sharing circuitry includes first current sharing circuitry coupled between the power delivery channels and a first set of input nodes of the controller, and second current sharing circuitry which is a portion of the controller and is coupled to the first set of input nodes, wherein the first current sharing circuitry is configured to assert channel feedback signals to the first set of input nodes, said channel feedback signals being indicative of channel portions of the output current, wherein each of the channel portions is that portion of the output current drawn from a different one of the power delivery channels, the second current sharing circuitry is configured to generate channel current error signals in response to the channel feedback signals, and the channel current error signals are indicative of the difference between an average of the channel portions and a different one of the channel portions, wherein the controller is configured to generate the power switch control signals in response to the channel current error signals and at least one output error signal indicative of the difference between the output potential and the reference potential, whereby the power switch control signals cause the converter to assert the output potential with reduced differences among the channel portions of the output current.

2. The DC-to-DC converter of claim 1, wherein the channel feedback signals are voltage signals and the second current sharing circuitry comprises:

a set of voltage-to-current converters, each having an input coupled to a different one of the first set of input nodes, configured to generate channel current signals indicative of the individual channel portions in response to the channel feedback signals;

current mirror circuitry coupled to the voltage-to-current converters to receive a first subset of the channel current signals and configured to produce average current signals in response to the first subset of the channel current signals, wherein each of the average current signals is indicative of the average of the channel portions; and

additional current mirror circuitry coupled to receive the average current signals and a second subset of the channel current signals and configured to generate the channel current error signals in response thereto.

3. The DC-to-DC converter of claim 2, wherein each of the voltage-to-current converters has a first output coupled to the current mirror circuitry and a second output coupled to the additional current mirror circuitry, each of the first subset of the channel current signals is asserted at the first output of one of the voltage-to-current converters and each of the second subset of the channel current signals is asserted at the second output of one of the voltage-to-current converters.

4. The DC-to-DC converter of claim 2, wherein the current mirror circuitry comprises:

a first current mirror which generates a first current proportional to a sum of the channel current signals in the first subset; and

second current mirror circuitry, coupled to the first current mirror, and configured to produce the average current signals in response to the first current.

5. The DC-to-DC converter of claim 2, wherein the controller also includes:

oscillator circuitry configured to generate a set of ramped voltage signals; and

comparator circuits, each having a first input coupled to receive a different one of the channel current error signals and a comparator having an input coupled to receive a different one of the ramped voltage signals, wherein the comparator circuits have outputs at which they assert pulse width modulated signals, wherein each of the comparator circuits is configured to generate a different one of the pulse width modulated signals in response to comparison of the potential at its first input with the potential at the input of the comparator thereof.

6. The DC-to-DC converter of claim 5, wherein the at least one output error signal is a set of error currents each indicative of the difference between the output potential and the reference potential, and the controller also comprises:

output error signal circuitry, coupled to the feedback input and the at least one reference input, and configured to generate the set of error currents in response to the feedback signal and the reference potential; and

wherein the additional current mirror circuitry comprises a set of current mirror circuits, each of said current mirror circuits comprising;

a first MOSFET device having a gate and a channel; and

a second MOSFET device having a gate coupled to the gate of the first MOSFET device, and a channel through which a channel current flows, wherein the channel current in the second MOSFET device of each of the current mirror circuits of the additional current mirror circuitry is equal to a different one of the channel current signals, and the first MOSFET device of each of the current mirror circuits of the additional current mirror circuitry is coupled to the output error signal circuitry and the current mirror circuitry such that a portion of the sum of one of the error currents and one of the average current signals flows through the channel thereof.

7. The DC-to-DC converter of claim 6, wherein said portion of the sum of one of the error currents and one of the average current signals flowing through the channel of the first MOSFET device of said each of the current mirror circuits of the additional current mirror circuitry is equal to said different one of the channel current signals flowing through the channel of the second MOSFET device of said each of the current mirror circuits of the additional current mirror circuitry.

8. The DC-to-DC converter of claim 5, wherein the controller also comprises:

logic and gate driver circuitry coupled to the comparator circuits to receive the pulse width modulated signals, and configured to generate the pulse width modulated power switch control signals in response to said pulse width modulated signals.

9. The DC-to-DC converter of claim 1, wherein the controller is configured so that each of the channel current error signals is proportional to said difference between the average of the channel portions and said different one of the channel portions with a proportionality constant determined by an external control signal applied to the controller.

10. The DC-to-DC converter of claim 1, wherein said switching controller is implemented as an integrated circuit, and the feedback circuitry and the first current sharing circuitry are external to said integrated circuit.

11. The DC-to-DC converter of claim 1, wherein said switching controller is implemented as a portion of an integrated circuit.

12. A switching controller for use in a DC-to-DC converter, having an input node for receiving an input potential and an output node at which the converter asserts an output potential, and configured so that when a load is coupled to the output node, the load draws an output current from said output node, wherein the switching controller is configured to generate at least two pulse width modulated power switch control signals and has a feedback input, said DC-to-DC converter having multiple power delivery channels each including a power switch coupled to the controller for receiving a different one of the pulse width modulated power switch control signals, and feedback circuitry configured to assert to the feedback input of the controller a feedback signal indicative of the output potential, said DC-to-DC converter also having circuitry configured to produce channel feedback signals indicative of channel portions of the output current, each of the channel portions being a portion of the output current drawn from a different one of the power delivery channels, said controller comprising:

current sharing circuitry including a first set of input nodes for receiving the channel feedback signals, and circuitry coupled to the first set of input nodes and configured to generate at least one average current error signal and at least two channel current error signals in response to the channel feedback signals, wherein each said average current signal is indicative of an average of the channel portions, and each of the channel current error signals is indicative of the difference between the average of the channel portions and a different one of the reference portions; and

control signal generating circuitry including at least one input coupled to receive at least one signal indicative of a reference potential, the control signal generating circuitry being configured to generate at least one output error signal indicative of the difference between the output potential and the reference potential and to generate the power switch control signals in response to the channel current error signals and said at least one output error signal, whereby the power switch control signals cause the DC-to-DC converter to assert the output potential with reduced differences among the channel portions of the output current.

13. The controller of claim 12, wherein the channel feedback signals are voltage signals, the at least one average current error signal is a set of average current error signals, and the current sharing circuitry comprises:

a set of voltage-to-current converters, each having an input coupled to a different one of the first set of input nodes, configured to generate channel current signals indicative of the individual channel portions in response to the channel feedback signals;

current mirror circuitry coupled to receive a first subset of the channel current signals and configured to produce the average current signals in response to the first subset of the channel current signals; and

additional current mirror circuitry coupled to receive the average current signals and a second subset of the channel current signals and configured to generate the channel current error signals in response thereto.

14. The controller of claim 13, wherein each of the voltage-to-current converters has a first output coupled to the current mirror circuitry and a second output coupled to the additional current mirror circuitry, each of the first subset of the channel current signals is asserted at the first output of one of the voltage-to-current converters and each of the second subset of the channel current signals is asserted at the second output of one of the voltage-to-current converters.

15. The controller of claim 13, wherein the current mirror circuitry comprises:

a first current mirror which generates a first current proportional to a sum of the channel current signals in the first subset; and

second current mirror circuitry, coupled to the first current mirror, and configured to produce the average current signals in response to the first current.

16. The controller of claim 13, also including:

oscillator circuitry configured to generate a set of ramped voltage signals, and

wherein the control signal generating circuitry includes comparator circuits, each having a first input coupled to receive a different one of the channel current error signals and a comparator having an input coupled to receive a different one of the ramped voltage signals, wherein the comparator circuits have outputs at which they assert pulse width modulated signals, wherein each of the comparator circuits is configured to generate a different one of the pulse width modulated signals in response to comparison of the potential at its first input with the potential at the input of the comparator thereof.

17. The controller of claim 16, wherein the at least one output error signal is a set of error currents each indicative of the difference between the output potential and the reference potential, and wherein the control signal generating circuitry also comprises output error signal circuitry, coupled to the feedback input and the at least one reference input, and configured to generate the set of error currents in response to the feedback signal and the reference potential, and

wherein the additional current mirror circuitry comprises a set of current mirror circuits, each of said current mirror circuits comprising:

a first MOSFET device having a gate and a channel; and

a second MOSFET device having a gate coupled to the gate of the first MOSFET device, and a channel through which a channel current flows, the channel current in the second MOSFET device of each of the current mirror circuits of the additional current mirror circuitry being equal to a different one of the channel current signals, wherein the first MOSFET device of each of the current mirror circuits of the additional current mirror circuitry is coupled to the output error signal circuitry and the current mirror circuitry such that a portion of the sum of one of the error currents and one of the average current signals flows through the channel thereof.

18. The controller of claim 17, wherein said portion of the sum of one of the error currents and one of the average current signals flowing through the channel of the first MOSFET device of each of the current mirror circuits of the additional current mirror circuitry is equal to said different one of the channel current signals flowing through the channel of the second MOSFET device of said each of the current mirror circuits of the additional current mirror circuitry.

19. The controller of claim 16, wherein the control signal generating circuitry also comprises:

logic and gate driver circuitry coupled to the comparator circuits to receive the pulse width modulated signals, and configured to generate the pulse width modulated power switch control signals in response to said pulse width modulated signals.

20. The controller of claim 12, wherein the current sharing circuitry is configured so that each of the channel current error signals is proportional to said difference between the average of the channel portions and said different one of the channel portions with a proportionality constant determined by an external control signal applied to said current sharing circuitry.

21. The controller of claim 12, wherein said switching controller is implemented as an integrated circuit.

22. The controller of claim 12, wherein said switching controller is implemented as a portion of an integrated circuit.

23. A method for generating pulse width modulated power switch control signals for use in a DC-to-DC converter which asserts an output potential at an output node in response to an input signal and the pulse width modulated power switch control signals, wherein the DC-to-DC converter is configured so that when a load is coupled to the output node, the load draws an output current from said output node, and the DC-to-DC converter has multiple power delivery channels each including a power switch coupled for receiving a different one of the pulse width modulated power switch control signals, said method comprising the steps of:

(a) generating at least one average current error signal and at least two channel current error signals in response to channel feedback signals, wherein the channel feedback signals are indicative of channel portions of the output current, each of the channel portions being a portion of the output current drawn from a different one of the power delivery channels, wherein each said average current signal is indicative of an average of the channel portions, and each of the channel current error signals is indicative of the difference between the average of the channel portions and a different one of the reference portions;

(b) generating at least one output error signal indicative of the difference between the output potential and a reference potential; and

(c) generating the power switch control signals in response to the channel current error signals and said at least one output error signal, whereby the power switch control signals are useful to cause the DC-to-DC converter to assert the output potential with reduced differences among the channel portions of the output current.

24. The method of claim 23, wherein the channel feedback signals are voltage signals, the at least one average current error signal is a set of average current error signals, and step (a) includes the steps of:

(d) generating channel current signals indicative of the individual channel portions in response to the channel feedback signals;

(e) employing current mirror circuitry to produce the average current signals in response to a first subset of the channel current signals; and

(f) employing additional current mirror circuitry to generate the channel current error signals in response to the average current error signals and a second subset of the channel current signals.

25. The method of claim 24, wherein step (e) includes the steps of:

employing a first current mirror to generate a first current proportional to a sum of the channel current signals in the first subset; and

employing second current mirror circuitry to produce the average current signals in response to the first current.

26. The method of claim 23, wherein step (c) includes the steps of:

generating a set of ramped voltage signals;

producing a set of error voltages, each proportional to the sum of the difference between the output potential and the reference potential and a voltage proportional to the difference between said average current error signal and a different one of the channel current error signals; and

generating pulse width modulated signals, each in response to comparison of a different one of the ramped voltage signals with a different one of the error voltages.

27. The method of claim 26, also including the step of:

employing logic and gate driver circuitry to generate the pulse width modulated power switch control signals in response to said pulse width modulated signals.

28. A method for performing DC-to-DC conversion using a DC-to-DC converter, having multiple power delivery channels connected in parallel between and input node and an output node, each of the channels including a power switch configured to operate under control of a different one of a set of pulse width modulated power switch control signals, to assert an output potential at the output node in response to an input signal at the input node and said set of pulse width modulated power switch control signals, while a load coupled to the output node draws an output current from said output node, said method comprising the steps of:

(a) generating at least one average current error signal and at least two channel current error signals in response to channel feedback signals, wherein the channel feedback signals are indicative of channel portions of the output current, each of the channel portions being a portion of the output current drawn from a different one of the power delivery channels, wherein each said average current signal is indicative of an average of the channel portions, and each of the channel current error signals is indicative of the difference between the average of the channel portions and a different one of the reference portions;

(b) generating at least one output error signal indicative of the difference between the output potential and a reference potential; and

(c) generating the power switch control signals in response to the channel current error signals and said at least one output error signal, whereby the power switch control signals are useful to cause the DC-to-DC converter to assert the output potential with reduced differences among the channel portions of the output current.

29. The method of claim 28, wherein the channel feedback signals are voltage signals, the at least one average current error signal is a set of average current error signals, and step (a) includes the steps of:

(d) generating channel current signals indicative of the individual channel portions in response to the channel feedback signals;

(e) employing current mirror circuitry to produce the average current signals in response to a first subset of the channel current signals; and

(f) employing additional current mirror circuitry to generate the channel current error signals in response to the average current error signals and a second subset of the channel current signals.

30. The method of claim 29, wherein step (e) includes the steps of:

employing a first current mirror to generate a first current proportional to a sum of the channel current signals in the first subset; and

employing second current mirror circuitry to produce the average current signals in response to the first current.

31. The method of claim 28, wherein step (c) includes the steps of:

generating a set of ramped voltage signals;

producing a set of error voltages, each proportional to the sum of the difference between the output potential and the reference potential and a voltage proportional to the difference between said average current error signal and a different one of the channel current error signals; and

generating pulse width modulated signals, each in response to comparison of a different one of the ramped voltage signals with a different one of the error voltages.

32. The method of claim 31, also including the step of:

employing logic and gate driver circuitry to generate the pulse width modulated power switch control signals in response to said pulse width modulated signals.