Programmable interconnect matrix architecture for complex programmable logic device

• US 6,137,308 A
• Filed: 01/20/1998
• Issued: 10/24/2000
• Est. Priority Date: 01/20/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nayak, Anup
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/009,569
• Time in Patent Office: 1,008 Days
• Field of Search: 326/38, 326/39, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Routing an input signal to an output of a programmable interconnect matrix is accomplished via multi-level routing architecture. The routing may include selecting the input signal from a number of input signals at a first level of the routing architecture to provide an intermediate signal. The intermediate signal may then be selected at a second level of the routing architecture to provide the output signal. Selecting the input signal and/or the intermediate signal may be accomplished by programming one or more mutliplexers. In a further embodiment, the method includes dividing a plurality of input signals into segments, each segment including a number of the plurality input signals. From the segments, at least one of the input signals may be selected to produce the intermediate signal. Further still, a method of interconnecting signals by coupling an input of a connection circuit of a programmable logic device to an output thereof through a multi-level routing architecture within the connection circuit is provided. The coupling may be accomplished by first coupling the input to a first intermediate signal path at a first level of the multi-level routing architecture and then coupling the intermediate signal path to the output at a second level of the multi-level routing architecture. In each case, the coupling may be accomplished by appropriate selection using one or more multiplexers at the various levels of the multi-level routing architecture.

Claims

1. A method, comprising routing an input signal to an output of a programmable interconnect matrix via a multi-level routing architecture by first selecting the input signal at a first one of a first number of switching elements of a first level of the multi-level routing architecture to produce an intermediate signal and then selecting the intermediate signal from among a number of inputs equal to the first number of switching elements at a second switching element of a second level of the multi-level routing architecture.

2. The method of claim 1 wherein the step of selecting the input signal comprises programming a multiplexer to select the input signal.

3. The method of claim 2 wherein the step of selecting the intermediate signal comprises programming a second multiplexer to select the intermediate signal .

4. The method of claim 1 wherein the step of selecting the intermediate signal comprises programming a multiplexer to select the intermediate signal.

5. A method, comprising:

dividing a plurality of input signals into segments, each segment comprising a number of the plurality of input signals;

selecting from the segments at a first level of a multi-level routing architecture of a programmable interconnect matrix in which switching succeeding levels have as many inputs as elements of immediately preceding levels have outputs at least one of the input signals to produce an intermediate signal; and

selecting the intermediate signal as an output signal from the programmable interconnect matrix.

6. The method of claim 5 wherein the step of selecting from the segments comprises programming a first multiplexer to select the at least one of the input signals.

7. The method of claim 6 wherein the step of selecting the intermediate signal comprises programming a second multiplexer to select the intermediate signal.

8. The method of claim 5 wherein a plurality of intermediate signals are produced from the segments and further comprising selecting additional output signals from the programmable interconnect matrix from the intermediate signals.

9. The method of claim 8 wherein the step of selecting additional output signals comprises programming one or more multiplexers to select desired ones of the additional intermediate signals.

10. A method of interconnecting signals, comprising coupling an input of a programmable interconnect matrix of a programmable logic device to an output of the programmable interconnect matrix through a multi-level routing architecture within the programmable interconnect matrix in which succeeding levels of the multi-level architecture include switching elements having a number of inputs equal to a number of outputs if switching elements of an immediately preceding level of the multi-level architecture.

11. The method of claim 10 wherein said step of coupling the input to the output comprises coupling the input to a first intermediate signal path at a first level of the multi-level routing architecture.

12. The method of claim 11 wherein the step of coupling the input to the output further comprises coupling the intermediate signal path to the output at a second level of the mutli-level routing architecture.

13. The method of claim 12 wherein the step of coupling the input to the intermediate signal path comprises selecting an input of a first multiplexer.

14. The method of claim 13 wherein the step of coupling the intermediate signal path to the comprises selecting an input of a second multiplexer.