Resistive pull-up device for I/O pin

• US 6,137,313 A
• Filed: 05/18/1998
• Issued: 10/24/2000
• Est. Priority Date: 06/20/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation), International Trade Associates, Inc.
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, White, Thomas H.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/080,539
• Time in Patent Office: 890 Days
• Field of Search: 326/57, 326/82, 326/83, 326/112, 326/119, 326/121, 326/30, 326/86
• US Class Current: 326/83
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

Various embodiments for improved I/O pin pull-up circuitry are disclosed. The pull-up devices according to the present invention minimize dissipation of crowbar current when the I/O pin is tri-stated. Circuit techniques are disclosed for minimizing the crowbar current as well as making the circuit high voltage tolerant.

Claims

1. A circuit formed in a semiconductor substrate comprising:

an I/O terminal;

an I/O circuit coupled to the I/O terminal; and

a pull-up circuit coupled to the I/O terminal, the pull-up circuit including;

a pull-up transistor formed in a well region inside the substrate;

a second transistor formed in the well region coupling in series with the pull-up transistor; and

a switching bias circuit configured to bias the well region to either a supply voltage or the voltage applied to the I/O terminal;

wherein the gate terminal of the pull-up transistor is coupled to ground; and

wherein the gate terminal of the second transistor is coupled to the I/O terminal.

2. The circuit of claim 1 wherein the pull-up transistor and the second transistor are p-channel transistors formed in n-type well regions.

3. The circuit of claim 2 wherein the gate terminal of the pull-up transistor couples to ground.

4. The circuit of claim 1 wherein the switching bias circuit is configured to bias the well region of the second transistor to either the supply voltage or the voltage applied to the I/O terminal.

5. The circuit of claim 4 wherein the pull-up transistor and the second transistor are formed inside the same n-type well region.

6. The circuit of claim 5 wherein the switching bias circuit is configured to bias the n-type well region to the higher of the power supply voltage or the voltage on the I/O terminal.

7. The circuit of claim 2 wherein the second transistor is diode-connected and is a substantially weak transistor comprising a channel that is longer than the minimum channel length to minimize its ON current.

8. The circuit of claim 7 wherein the I/O circuit comprises an input p-channel transistor having a gate terminal coupled to the I/O terminal and a current-carrying terminal coupled to the power supply terminal.

9. The circuit of claim 8 wherein a channel length of the pull-up transistor is substantially smaller than a channel length of the input p-channel transistor.

10. The integrated circuit of claim 7 wherein a width of the pull-up transistor is equal to or larger than a width of the input p-channel transistor.