Input receiver circuit

• US 6,137,320 A
• Filed: 03/10/1999
• Issued: 10/24/2000
• Est. Priority Date: 03/18/1998
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Takai, Yasuhiro
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/266,067
• Time in Patent Office: 594 Days
• Field of Search: 327/379, 327/387, 327/388, 327/403, 327/404, 327/407, 327/408, 327/409, 327/410, 327/108, 327/50, 327/51, 327/52, 327/53, 327/54, 327/55, 327/56, 327/77, 327/78, 327/79, 327/80, 327/81 , 327/88
• US Class Current: 327/56
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers

Abstract

An input receiver circuit which is capable of reducing a difference between a propagation time at the rise-up and that at the fall of an input signal and is suitably used for semiconductor memory devices. The input receiving circuit comprises a node, six N channel (N-ch) MOS transistors and two P channel (P-ch) MOS transistors. The first and second N-ch transistors receive an activation signal and have grounded sources. The third and fourth N-ch transistors receive the first and second signal and have sources connected to the drains of the first and second N-ch transistors, respectively. The fifth and sixth N-ch transistors have gates connected to the node and are provided in parallel to the third and fourth N-ch transistors, respectively. Sources of the first and second P-ch transistors are supplied with the power source voltage. Drains of the first and second P-ch transistors are connected to the drains of the third and fourth N-ch transistors, respectively. Gates of the first and second P-ch transistors are connected to the node. The second P-ch transistor outputs a drain voltage as an output signal.

Claims

1. An input receiver circuit comprising:

a first N channel MOS transistor having a gate supplied with an activation signal and a source connected to a ground potential;

a second N channel MOS transistor having a gate supplied with said activation signal and a source connected to the ground potential;

a third N channel MOS transistor having a gate supplied with a first signal and a source connected to a drain of said first N channel MOS transistor;

a fourth N channel MOS transistor having a gate supplied with a second signal and a source connected to a drain of said second N channel MOS transistor;

a node;

a fifth N channel MOS transistor having a source connected to the source of said third N channel MOS transistor, a drain connected to a drain of said third N channel MOS transistor, and a gate connected to said node;

a sixth N channel MOS transistor having a source connected to the source of said fourth N channel MOS transistor, a drain connected to a drain of said fourth N channel MOS transistor, and a gate connected to said node;

a first P channel MOS transistor having a source supplied with a power source voltage, a drain connected to the drain of said third N channel MOS transistor, and a gate connected to said node; and

a second P channel MOS transistor having a source supplied with the power source voltage, a drain connected to the drain of said fourth N channel MOS transistor, and a gate connected to said node, the second P channel MOS transistor outputting a drain voltage as an output signal.

2. The input receiver circuit according to claim 1, wherein said activation signal becomes a high level potential when said input receiver circuit is to be activated, and said activation signal becomes a ground potential when said input receiver circuit is to be inactivated.

3. The input receiver circuit according to claim 1, wherein said first signal is a reference voltage signal, said second signal is an input signal, and said output signal changes depending on a level of said input signal.

4. The input receiver circuit according to claim 1, wherein said first and second signals are in a complementary relationship.

5. The input receiver circuit according to claim 1, further comprising:

a third P channel MOS transistor having a gate applied with said first signal, a source connected to the source of said first P channel MOS transistor, and a drain connected to the drain of said first P channel MOS transistor; and

a fourth P channel MOS transistor having a gate applied with said second signal, a source connected to the source of said second P channel MOS transistor, and a drain connected to the drain of said second P channel MOS transistor.

6. The input receiver circuit according to claim 1, wherein a transistor size ratio of said third N channel MOS transistor to said fifth N channel MOS transistor is approximately 2:

1.

7. An input receiver circuit comprising:

a first N channel MOS transistor having a gate supplied with an activation signal and a source connected to a ground potential;

a second N channel MOS transistor having a gate supplied with a first signal and a source connected to a drain of said first N channel MOS transistor;

a third N channel MOS transistor having a gate supplied with a second signal and a source connected to a drain of said first N channel MOS transistor;

a node;

a fourth N channel MOS transistor having a source connected to the source of said third N channel MOS transistor, a drain connected to said second N channel MOS transistor, and a gate connected to said node;

a fifth N channel MOS transistor having a source connected to the source of said third N channel MOS transistor, a drain connected to a drain of said third N channel MOS transistor, and a gate connected to said node;

a first P channel MOS transistor having a source supplied with a power source voltage, a drain connected to the drain of said second N channel MOS transistor, and a gate connected to said node; and

a second P channel MOS transistor having a source supplied with the power source voltage, a drain connected to the drain of said third N channel NOS transistor, and a gate connected to said node, said second P channel MOS transistor outputting a drain voltage as an output signal.

8. The input receiver circuit according to claim 7, wherein said activation signal becomes a high level potential when said input receiver circuit is to be activated, and said activation signal becomes a ground potential when said input receiver circuit is to be inactivated.

9. The input receiver circuit according to claim 7, wherein said first signal is a reference voltage signal, said second signal is an input signal, and said output signal changes depending on a level of said input signal.

10. The input receiver circuit according to claim 7, wherein said first and second signals are in a complementary relationship.

11. The input receiver circuit according to claim 7, further comprising:

a third P channel MOS transistor having a gate applied with said first signal, a source connected to the source of said first P channel MOS transistor, and a drain connected to the drain of said first P channel MOS transistor; and

a fourth P channel MOS transistor having a gate applied with said second signal, a source connected to the source of said second P channel MOS transistor, and a drain connected to the drain of said second P channel MOS transistor.

12. The input receiver circuit according to claim 7, wherein a transistor size ratio of said second N channel MOS transistor to said fourth N channel MOS transistor is approximately 2:

1.

13. An input receiver circuit comprising:

a first MOS transistor of one conductivity type having a gate supplied with an activation signal and a source connected to a ground potential;

a second MOS transistor of the one conductivity type having a gate supplied with said activation signal and a source connected to the ground potential;

a third MOS transistor of the one conductivity type having a gate supplied with a first signal and a source connected to a drain of said first MOS transistor;

a fourth MOS transistor of the one conductivity type having a gate supplied with a second signal and a source connected to a drain of said second MOS transistor;

a node;

a fifth MOS transistor of the one conductivity type having a source connected to the source of said third MOS transistor, a drain connected to a drain of said third MOS transistor, and a gate connected to said node;

a sixth MOS transistor of the one conductivity type having a source connected to the source of said fourth MOS transistor, a drain connected to a drain of said fourth MOS transistor, and a gate connected to said node;

a seventh MOS transistor of an opposite conductivity type having a source supplied with a power source voltage, a drain connected to the drain of said third MOS transistor, and a gate connected to said node; and

an eighth MOS transistor of the opposite conductivity type having a source supplied with the power source voltage, a drain connected to the drain of said fourth MOS transistor, and a gate connected to said node, the eighth MOS transistor outputting a drain voltage as an output signal.

14. An input receiver circuit comprising:

a first MOS transistor of one conductivity type having a gate supplied with an activation signal and a source connected to a ground potential;

a second MOS transistor of the one conductivity type having a gate supplied with a first signal and a source connected to a drain of said first MOS transistor;

a third MOS transistor of the one conductivity type having a gate supplied with a second signal and a source connected to a drain of said first MOS transistor;

a node;

a fourth MOS transistor of the one conductivity type having a source connected to the source of said third MOS transistor, a drain connected to said second MOS transistor, and a gate connected to said node;

a fifth MOS transistor of the one conductivity type having a source connected to the source of said third MOS transistor, a drain connected to a drain of said third MOS transistor, and a gate connected to said node;

a sixth MOS transistor of an opposite conductivity type having a source supplied with a power source voltage, a drain connected to the drain of said second MOS transistor, and a gate connected to said node; and

a seventh MOS transistor of the opposite conductivity type having a source supplied with the power source voltage, a drain connected to the drain of said third MOS transistor, and a gate connected to said node, said seventh MOS transistor outputting a drain voltage as an output signal.