Oscillator receiving variable supply voltage depending on substrate voltage detection

• US 6,137,335 A
• Filed: 06/03/1999
• Issued: 10/24/2000
• Est. Priority Date: 07/29/1996
• Status: Expired due to Term

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Townsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/324,932
• Time in Patent Office: 509 Days
• Field of Search: 327/270, 327/276, 327/278, 327/281, 327/534, 327/537, 327/536
• US Class Current: 327/281
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

Claims

1. An oscillator for controlling semiconductor devices comprising:

a power supply circuit coupled to a high voltage, a substrate voltage, and a ground voltage, and configured to generate a first voltage at a power supply node when the substrate voltage is above a selected value and to generate a second voltage at the power supply node when the substrate voltage is below the selected value; and

an odd plurality of oscillator stages for generating an oscillator signal at a selected frequency, each oscillator stage comprising;

an input node for receiving a control signal which alternates between third and fourth voltage values;

a first switch, coupled to the power supply node and to the input node, for conducting current when the control signal differs from the supply voltage signal by a first threshold voltage;

a second switch, coupled to the power supply node and to the input node, for conducting current when the control signal differs from the ground voltage by a second threshold voltage;

wherein the first and second switches conduct current in a substantially mutually exclusive manner as the control signal varies from the third voltage value to the fourth voltage value.

2. The oscillator according to claim 1 wherein the first switch comprises a first transistor having a first current flowing terminal, a second current flowing terminal and a control terminal;

wherein the second switch comprises a second transistor having a first current flowing terminal, a second current flowing terminal, and a control terminal;

wherein the first current flowing terminal of the first transistor is coupled to the power supply node;

wherein the second current flowing terminal of the first transistor is coupled to the first current flowing terminal of the second transistor at an output node;

wherein the control terminal of the first transistor is coupled to the input node;

wherein the control terminal of the second transistor is coupled to the input node; and

wherein the second current flowing terminal of the second transistor is coupled to a ground potential.

3. The oscillator according to claim 2 wherein the output node of each oscillator stage is coupled to the input node of a succeeding oscillator stage so that the plurality of oscillator stages are serially connected.

4. The oscillator according to claim 3 wherein the power supply circuit comprises a voltage divider comprising a plurality of resistive elements serially coupled between the high voltage and the ground voltage, and wherein one of said plurality of resistive elements is switchable in response to the substrate voltage.

5. The oscillator according to claim 4 wherein the switchable resistive element comprises a third transistor having a first current flowing terminal coupled to the voltage divider, a second current flowing terminal coupled to the ground voltage, and a control terminal coupled to the substrate voltage.

6. The oscillator according to claim 4 wherein the plurality of resistive elements comprises:

a first PMOS transistor having a source terminal coupled to the high voltage, a drain terminal coupled to the power supply node, and a gate terminal coupled to the ground voltage;

two diode-connected NMOS transistors serially coupled between the power supply node and a second node;

a diode-connected PMOS transistor coupled between the second node and a third node;

a second PMOS transistor having a source terminal coupled to the N well of said second PMOS transistor and to the third node, a gate terminal coupled to the substrate voltage, and a drain terminal coupled to the ground voltage, said second PMOS transistor comprising the switchable resistive element.

7. The oscillator according to claim 5 wherein a fifth transistor is disposed between the power supply node and the oscillator, said fifth transistor having a first current flowing terminal coupled to the high voltage, a control terminal coupled to the power supply node, and a second current flowing terminal coupled to the oscillator.

8. The oscillator according to claim 7 wherein the first switch comprises a third PMOS transistor and the second switch comprises a third NMOS transistor;

the third PMOS transistor having a source terminal coupled to the second current flowing terminal of the fifth transistor, a gate terminal coupled to the input terminal, and a drain terminal; and

the third NMOS transistor having a source terminal coupled to the ground potential, a drain terminal coupled to the drain terminal of the third PMOS transistor, and a gate terminal coupled to the input node.

9. A variable frequency oscillator comprising:

an odd plurality of oscillator stages, each oscillator stage including;

a first transistor having a first current flowing terminal coupled to a voltage source, a control terminal coupled to an input node which receives an input signal which alternates between first and second voltage values, and a second current flowing terminal;

a second transistor having a first current flowing terminal coupled to the second current flowing terminal of the first transistor at an output node, a second current flowing terminal coupled to a ground potential, and a control terminal coupled to the input node;

wherein the first and second transistors conduct current in a substantially mutually exclusive manner so that a signal at the output node varies between third and fourth voltage values as the input signal varies from the first voltage value to the second voltage value;

wherein the output node of each oscillator stage is coupled to the input node of a succeeding oscillator stage so that the plurality of oscillator stages are serially connected;

wherein each oscillator stage further comprises;

frequency select means for receiving a frequency select signal; and

signal rate increasing means, coupled to the output node and to the frequency select means, for increasing a rate of change of the signal at the output node between the third and fourth voltage values in response to the frequency select signal.

10. The oscillator according to claim 9 wherein the signal rate increasing means comprises:

a third transistor having a first current flowing terminal coupled to the voltage source, a control terminal coupled to the input node, and a second current flowing terminal coupled to the output node;

a fourth transistor having a first current flowing terminal coupled to the output node, a control terminal coupled to the input node, and a second current flowing terminal coupled to the ground potential;

wherein the third and fourth transistors are more conductive than the first and second transistors;

wherein the third and fourth transistors conduct current in a substantially mutually exclusive manner as the control signal varies from the first voltage value to the second voltage value so that the third transistor conducts when the first transistor conducts and the fourth transistor conducts when the second transistor conducts; and

transistor control means, coupled to the third and fourth transistors and to the frequency select means, for enabling the operation of the third and fourth transistors in response to the frequency select signal.

11. The oscillator according to claim 10 wherein the transistor control means in each oscillator stage comprises:

a fifth transistor having a first current flowing terminal coupled to the voltage source, a second current flowing terminal coupled to the first current flowing terminal of the third transistor, and a control terminal coupled for receiving the frequency select signal;

a sixth transistor having a first current flowing terminal coupled to the second current flowing terminal of the fourth transistor, a second current flowing terminal coupled to the ground potential, and a control terminal coupled for receiving the frequency select signal; and

wherein the fifth and sixth transistors are enabled for conducting current substantially simultaneously in response to the frequency select signal so that the third and fourth transistors may conduct current in response to the input signal.

12. An oscillator comprising:

a power supply circuit for generating a supply voltage signal; and

an oscillator circuit including an odd plurality of oscillator stages for generating an oscillator signal at a selected frequency, each oscillator stage comprising;

an input node for receiving a control signal which alternates between first and second voltage values;

a first switch, coupled to the power supply circuit and to the input node, for conducting current when the control signal differs from the supply voltage signal by a first threshold voltage;

a second switch, coupled to the power supply circuit and to the input node, for conducting current when the control signal differs from a ground voltage by a second threshold voltage;

wherein the first and second switches conduct current in a substantially mutually exclusive manner as the control signal varies from the first voltage value to the second voltage value;

wherein the supply voltage signal has a voltage approximately equal to the magnitude of the first threshold voltage plus the magnitude of the second threshold voltage.

13. The oscillator according to claim 12 wherein the first switch comprises a first transistor having a first current flowing terminal, a second current flowing terminal and a control terminal;

wherein the second switch comprises a second transistor having a first current flowing terminal, a second current flowing terminal, and a control terminal;

wherein the first current flowing terminal of the first transistor is coupled to the power supply circuit;

wherein the second current flowing terminal of the first transistor is coupled to the first current flowing terminal of the second transistor at an output node;

wherein the control terminal of the first transistor is coupled to the input node;

wherein the control terminal of the second transistor is coupled to the input node; and

wherein the second current flowing terminal of the second transistor is coupled to a ground potential.

14. The oscillator according to claim 13 wherein the output node of each oscillator stage is coupled to the input node of a succeeding oscillator stage so that the plurality of oscillator stages are serially connected.

15. The oscillator according to claim 14 wherein the first switch comprises a PMOS transistor and the second switch comprises a NMOS transistor;

the PMOS transistor having a source terminal coupled to the power supply circuit, a gate terminal coupled to the input node, and a drain terminal; and

the NMOS transistor having a source terminal coupled to the ground potential, a drain terminal coupled to the drain terminal of the PMOS transistor, and a gate terminal coupled to the input node.

16. The oscillator according to claim 15 wherein the power supply voltage signal has a voltage approximately equal to the magnitude of the first threshold voltage plus the magnitude of the second threshold voltage.

17. An oscillator circuit comprising:

a power supply node adapted to receive a power supply signal, wherein said power supply signal has a voltage value approximately equal to a logic high voltage;

a low voltage generator coupled to the power supply node and configured to generate at a first node a low voltage signal; and

a ring oscillator including an odd number of inverting stages coupled in a ring, with each inverting stage comprising a first PMOS transistor and a first NMOS transistor serially coupled between the first node and ground with commonly-coupled gate terminals;

wherein the low voltage signal is approximately equal to the sum of the absolute magnitude of a threshold voltage of the first PMOS transistor and a threshold voltage of the first NMOS transistor.

18. The oscillator circuit of claim 17 further comprising a voltage level translator coupled to the ring oscillator, wherein the voltage level translator is configured to translate a level of an output signal of the ring oscillator from the low voltage signal to the logic high power supply signal.

19. The oscillator circuit of claim 17 wherein the low voltage generator comprises:

a PMOS transistor having its source/drain terminals coupled between the power supply node and an intermediate node, and a gate terminal coupled to ground;

a plurality of serially-coupled transistors coupled between the intermediate node and ground; and

an NMOS transistor having a gate terminal coupled to the intermediate node, a first source/drain terminal coupled to the power supply node, and a second source/drain terminal coupled the first node.

20. The oscillator circuit of claim 19 wherein the plurality of serially-coupled transistors comprises first and second diode-coupled NMOS transistors and a diode-coupled PMOS transistor.

21. The oscillator circuit of claim 20 wherein the low voltage generator further comprises a PMOS transistor having source/drain terminals coupled between the serialy-coupled transistors and ground, and a gate terminal coupled to a negative voltage with respect to ground.

22. The oscillator circuit of claim 17 wherein each inverting stage of the ring oscillator further comprises a second PMOS transistor and a second NMOS transistor having commonly-coupled gate terminals and a commonly-coupled first source/drain terminals, the second PMOS transistor having a second source/drain terminal coupled to the first node via a first switch, and the second NMOS transistor having a second source/drain terminal coupled to ground via a second switch.

23. The oscillator circuit of claim 22 wherein the first switch is a PMOS transistor with a gate terminal coupled to a first frequency control signal, and the second switch is an NMOS transistor with a gate terminal coupled to a second frequency control signal.

24. The oscillator circuit of claim 23 wherein in a first mode of operation the first and second frequency control signals turn off the first and second switches, respectively, for a first frequency output, and

in a second mode of operation, the first and second frequency control signals turn on the first and second switches, respectively, for a second frequency output that is higher than the first frequency output.