High power high impedance microwave devices for power applications

• US 6,137,367 A
• Filed: 03/08/1999
• Issued: 10/24/2000
• Est. Priority Date: 03/24/1998
• Status: Expired due to Fees

• Current Assignee: Amcom Communications, Inc.
• Original Assignee: Amcom Communications, Inc.
• Inventors: Ezzedine, Amin, Huang, Ho C.
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/263,853
• Time in Patent Office: 596 Days
• Field of Search: 330/98, 330/99, 330/100, 330/302, 330/310, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/271 the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses capacitive isolation means, e.g. capacitors
• CPC Class Codes: H03F 2200/54 Two or more capacitor coupled amplifier stages in cascade
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03F 3/604 using FET's

Abstract

Simplified, efficient multiple-transistor power amplifiers provide high power and high impedance while avoiding the use of RF power divider and combiner circuits.

The input signal is directly applied to a first transistor, amplified, and supplied to the succeeding transistor, and so on, for amplification in series. Feedback is provided between the drain of the last transistor and the gates of all the transistors. Series connection of the transistors allows their power outputs and their output impedances to be summed, such that no RF output combiner is required.

In a first high voltage embodiment of the amplifier of the invention, e.g., as used for satellite transmission, bias voltage is provided in series.

In a second low voltage embodiment, suitable for use in cordless telephones and other battery-powered equipment, bias voltage V_ds is provided separately across the drain and source terminals of each transistor, through paired chokes.

Claims

1. An amplifier for amplifying an input signal, comprising:

a plurality of semiconductor amplifying elements, each comprising a control terminal to which a signal may be applied for controlling the flow of current between additional input and output terminals, and a source of bias voltage providing power for said amplifying elements,

said plurality of amplifying elements being connected in series, such that the output terminal of a first element of the series is connected to the input terminal of the next element of the series, and so on, the input signal being applied to the control terminal of the first element of the series, and the output terminal of the last element of the series being connected to an output circuit, and the output terminal of the last element of the series also being connected to the control terminals of each of the elements of the series, such that the output signal from the last element of the series is supplied to the control terminals of each of the elements of the series for feedback,

wherein capacitors are connected between the control terminals of each of the amplifying elements in the series except the first and ground, the value of each said capacitor being chosen to optimize the impedance of and power output by the corresponding amplifying elements;

wherein said source of bias voltage is connected to the output terminal of the last of said elements in said series through a choke, and wherein said bias voltage is provided to each of said elements by voltage-dividing resistors in series across the control terminals of said elements; and

wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through the same series-connected resistors used to supply bias voltage.

2. The amplifier of claim 1, wherein the control terminal of the first of said amplifying elements of the series is connected to a point maintained at a fixed potential through a choke, such that high-frequency input signal components are not grounded.

3. The amplifier of claim 1, further comprising an input matching network between the input terminal of said amplifier and the control terminal of the first amplifying element in said series, and an output matching network between the output terminal of the last amplifying element in the series and the output terminal of said amplifier.

4. The amplifier of claim 3, wherein said input and output matching networks comprise capacitors.

5. The amplifier of claim 1, wherein additional bias voltage is supplied separately to each of said amplifying elements.

6. The amplifier of claim 5, wherein the additional bias voltage is applied separately across the input and output terminals of each of said amplifying elements, and a choke is provided between at least the output terminal of each and the source of bias voltage.

7. The amplifier of claim 6, wherein a choke is also provided between the input terminals of all but the first of said amplifying elements in said series and ground.

8. The amplifier of claim 6, wherein capacitors are connected between the output and input terminals of adjoining elements of said series.

9. The amplifier of claim 6, wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through a string of series-connected resistors.

10. The amplifier of claim 1, wherein the value C_shunt of each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_source of the corresponding amplifying element, in accordance with the following equation:

space="preserve" listing-type="equation">Z.sub.source ≅

1/g.sub.m *(C.sub.gs +C.sub.shunt)/C.sub.shunt

where

Z_source is the impedance of the corresponding amplifying element;

g_m is the cell transconductance of the corresponding amplifying element;

C_gs is the gate to source cell capacitance; and

C_shunt is the value of the capacitance between the control terminal and ground.

11. A circuit for providing high-power, high-impedance amplification of a RF signal, comprising:

a plurality of amplifying elements, each comprising input, output, and control terminals,

said plurality of amplifying elements being connected in series, such that the output terminal of the first element in the series is connected to the input terminal of the second, and so on;

an input connection for applying a RF input signal to the control terminal of the first element in the series;

an output connection connected to the output terminal of the last element in the series, for applying an amplified RF output signal to a load;

a source of bias voltage operatively connected to each of said amplifying elements;

a feedback path for supplying a portion of the output signal to the control terminals of each of the elements in the series;

capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground, the value of each said capacitor being chosen to optimize the impedance of and power output by the corresponding amplifying element;

wherein said bias voltage is provided to each of said elements by voltage-dividing resistors in series across the control terminals of said elements; and

wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through the same series-connected resistors used to supply bias voltage.

12. The circuit of claim 11, wherein said source of bias voltage is connected to the output terminal of the last of said elements in said series through a choke.

13. The circuit of claim 11, further comprising an input matching network between said input connection and the control terminal of the first amplifying element in said series, and an output matching network between the output terminal of the last amplifying element in the series and said output connection.

14. The circuit of claim 13, wherein said input and output matching networks comprise capacitors.

15. The circuit of claim 11, wherein additional bias voltage is supplied separately to each of said amplifying elements.

16. The circuit of claim 15, wherein the additional bias voltage is applied separately across the input and output terminals of each of said amplifying elements, and a choke is provided between at least the output terminal of each and the source of bias voltage.

17. The circuit of claim 16, wherein capacitors are connected between the output and input terminals of adjacent elements in said series.

18. The circuit of claim 16, wherein a choke is also provided between the input terminals of all but the first of said amplifying elements in said series and ground.

19. The circuit of claim 15, wherein said output signal is supplied to the control terminals of each of the elements of the series for feedback through a set of series-connected resistors.

20. The circuit of claim 11, wherein the value C_shunt of each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_source of the corresponding amplifying element, in accordance with the following equation:

space="preserve" listing-type="equation">Z.sub.source ≅

1/g.sub.m *(C.sub.gs +C.sub.shun)/C.sub.shunt

where

Z_source is the impedance of the corresponding amplifying element;

g_m is the cell transconductance of the corresponding amplifying element;

C_gs is the gate to source cell capacitance; and

C_shunt is the value of the capacitance between the control terminal and ground.

21. A method for providing high-power, high-impedance amplification of an RF input signal, comprising the steps of:

connecting a plurality of amplifying elements, each comprising input, output, and control terminals, in series, such that the output terminal of the first element in the series is connected to the input terminal of the second, and so on;

applying an RF input signal to the control terminal of the first element in the series;

providing bias voltage to each of said amplifying elements, such that the input RP signal is amplified in each element;

connecting a load to the output terminal of the last element in the series, for applying an amplified RF output signal to the load;

feeding back a portion of the output signal to the control terminals of each of the elements in the series; and

wherein

capacitors are connected between the control terminals of each of said amplifying elements, except the first, and ground, the value of each of said capacitors being chosen to adjust the impedance of and power output by the corresponding amplifying element;

wherein said step of providing bias voltage to each of said amplifying elements is performed by providing a voltage V_dd greater than the desired bias voltage V_ds, and dividing V_dd into smaller voltages employing a plurality of series-connected resistors; and

wherein said plurality of series-connected resistors are connected across the control terminals of said amplifying elements, and wherein said portion of the output signal is also fed back thereby to the control terminals of said amplifying elements.

22. The method of claim 21, comprising the further step of providing additional bias voltage to each of said amplifying elements by supplying a desired bias voltage V_ds separately to each of said amplifying elements.

23. The method of claim 22, wherein a source of said desired bias voltage V_ds is connected to the output terminal of each of said amplifying elements through a choke.

24. The method of claim 23, wherein the input terminal of each amplifying elements except the first is connected through a choke to ground.

25. The method of claim 22, wherein capacitors are connected between he output and input terminals of adjoining ones of said amplifying elements.

26. The method of claim 21, wherein the value C_shunt of each of said capacitors connected between the control terminals of each of the amplifying elements in the series except the first and ground is chosen so as to optimize the impedance Z_source of the corresponding amplifying element, in accordance with the following equation:

space="preserve" listing-type="equation">Z.sub.source ≅

1/g.sub.m *(C.sub.gs +C.sub.shunt)/C.sub.shunt

where

Z_source is the impedance of the corresponding amplifying element;

g_m is the cell transconductance of the corresponding amplifying element;

C_gs is the gate to source cell capacitance; and

C_shunt is the value of the capacitance between the control terminal and ground.