Method for operating a non-volatile memory cell arrangement

• US 6,137,718 A
• Filed: 01/28/1999
• Issued: 10/24/2000
• Est. Priority Date: 08/01/1996
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Reisinger, Hans
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, HOAI V
• Application Number:
  US09/230,612
• Time in Patent Office: 635 Days
• Field of Search: 365/185.03, 365/185.28, 365/185.01, 257/324
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 2⁶ values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.

Claims

1. A method for operating a memory cell arrangement, comprising the steps of:

providing memory cells having MOS transistors;

providing said MOS transistors with a gate dielectric including a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer;

providing the first silicon oxide layer and the second silicon oxide layer each with a thickness of at least 3 nm;

using multi-value logic with more than two logic values to store information;

applying a respective quantity of charge assigned to the respective logic value to the gate dielectric by Fowler-Nordheim tunneling for writing a respective logic value of the more than two logic values to one of the memory cells; and

storing the respective quantity of charge in the gate dielectric, said quantity of charge effects a threshold voltage level of the MOS transistor which is assigned to the respective logic value.

2. The method as claimed in claim 1, further comprising the step of:

increasing an amount separating neighboring threshold voltage levels as the threshold voltage level increases.

3. The method as claimed in claim 1,

wherein a difference between thicknesses of the first silicon oxide layer and the second silicon oxide layer lies in a range between 0.5 nm and 1 nm,

wherein a smaller of the thicknesses of the first silicon oxide layer and of the second silicon oxide layer lies in a range between 3 nm and 6 nm,

wherein the silicon nitride layer has a thickness of at least 5 nm, and

wherein each of the MOS transistors has a gate electrode made of n-doped silicon.

4. The method as claimed in claim 3, further comprising the step of:

using multi-value logic with 2n values, where n is between 2 and 6.

5. The method as claimed in claim 1,

wherein a difference between thicknesses of the first silicon oxide layer and the second silicon oxide layer lies in a range between 0.5 nm and 1 nm,

wherein a smaller of the thicknesses of the first silicon oxide layer and of the second silicon oxide layer lies in a range between 3.2 and 4 nm,

wherein the silicon nitride layer has a thickness of at least 5 nm, and

wherein each of the MOS transistors has a gate electrode made of p⁺ -doped silicon.

6. The method as claimed in claim 5, wherein p⁺ -doped silicon in the gate electrode has a dopant concentration of at least 1×

10²⁰ cm^-3.

7. The method as claimed in claim 5, further comprising the step of:

using multi-value logic with 2n values, where n is between 2 and 3.