Variable scaling of 16-bit fixed point fast fourier forward and inverse transforms to improve precision for implementation of discrete multitone for asymmetric digital subscriber loops

• US 6,137,839 A
• Filed: 10/31/1996
• Issued: 10/24/2000
• Est. Priority Date: 05/09/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gatherer, Alan, Shaver, Donald P., Mannering, Dennis G.
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US08/742,226
• Time in Patent Office: 1,454 Days
• Field of Search: 375/222, 375/260, 375/377, 370/210
• US Class Current: 375/260
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 2025/03611 Iterative algorithms
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/4921 using quadrature encoding, e.g. carrierless amplitude-phase coding
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2655 Synchronisation arrangements
• CPC Class Codes: H04L 5/023 Multiplexing of multicarrier modulation signals multicarrier modulation H04L27/2601
• CPC Class Codes: H04L 5/1438 Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data

Abstract

A discrete multitone (DMT) digital subscriber loop (xDSL) telecommunication system has a transmitter portion including a bit encoder, inverse fast Fourier transform (FFT), parallel-to-serial converter, digital-to-analog converter and line driver for transmitting data signals to a twisted pair telephone line and a receiver portion including an analog-to-digital converter, serial-to-parallel converter, forward FFT and bit decoder for receiving data signals from the twisted pair telephone line. The FFT'"'"'s are implemented in 19-bit precision using a fixed point 16-bit processor. At each FFT stage, the number of sign bits in the FFT input data is examined to determine whether overflow is possible during multiply and add operations. The input data is downscaled by right shifting one or two bits if overflow is possible. If downscaling occurred, the output data is rescaled after completion of the FFT operation. If overflow is not possible, no scaling is done. By using variable scaling to downscale only when necessary, better overall precision is maintained.

Claims

1. In a discrete digital multitone (DMT) digital subscriber loop (xDSL) telecommunications system having a transmitter portion including a bit encoder, an inverse fast Fourier transform (IFFT), parallel-to-serial converter, digital-to-analog converter and line driver for transmitting data signals to a twisted pair telephone line and a receiver portion including an analog-to-digital converter, a serial-to-parallel converter, a forward fast Fourier transform (FFT) and a bit decoder for receiving data signals from the twisted pair telephone line, the IFFT and FFT being implemented in N-bit precision using a fixed point M-bit (M<

N) processor by downscaling input data at each IFFT and FFT stage to prevent fixed point values from overflowing during multiply and add operations of the processor;

the improvement comprising implementing the IFFT and FFT in fixed point M-bit processing using variable scaling including the following steps;

looking at data input to both the inverse FFT and forward FFT before each said IFFT and FFT stage to determine whether overflow is possible;

downscaling the FFT and IFFT input data by a given number of bits if the determination shows that overflow is possible;

leaving the FFT and IFFT input data unscaled if the determination shows that overflow is not possible;

maintaining track of whether downscaling was done;

rescaling data output from the FFT and IFFT at the completion of the FFT and IFFT operation if downscaling was done; and

leaving the FFT and IFFT output data unrescaled if downscaling was not done.

2. The improvement of claim 1, wherein determining whether overflow is possible is done by looking at the number of sign bits in the FFT and IFFT input data.

3. The improvement of claim 2, wherein downscaling is done by shifting the FFT and IFFT input data a given number of bits to the right.

4. The improvement of claim 3, wherein the given number of bits is two.

5. The improvement of claim 4, wherein the FFT and IFFT are implemented in 19-bit precision using fixed point 16-bit processing.

6. The improvement of claim 1, wherein downscaling is done by shifting the FFT and IFFT input data a given number of bits to the right.

7. The improvement of claim 6, wherein the given number of bits is two.

8. The improvement of claim 1, wherein the FFT and IFFT are implemented in 19-bit precision using fixed point 16-bit processing.

9. In a discrete digital multitone (DMT) digital subscriber loop (xDSL) telecommunications system having a transmitter portion including a bit encoder, an inverse fast Fourier transform (IFFT), parallel-to-serial converter, digital-to-analog converter and line driver for transmitting data signals to a twisted pair telephone line and a receiver portion including an analog-to-digital converter, a serial-to-parallel converter, a forward fast Fourier transform (FFT) and a bit decoder for receiving data signals from the twisted pair telephone line, the method of implementing at least one FFT in fixed point M-bit processing comprising the steps of:

looking at data input to at least one FFT stage to determine whether overflow during fixed point value multiply and add operations of the processor is possible during the FFT operation;

downscaling the FFT input by a given number of bits to prevent the possibility of overflow if the determination shows that overflow is possible;

leaving the FFT input data unscaled if the determination shows that overflow is not possible;

maintaining track of whether downscaling was done;

rescaling data output from the at least one FFT at the completion of the FFT operation if downscaling was done; and

leaving the FFT output data unrescaled if downscaling was not done.

10. The improvement of claim 9, wherein determining whether overflow is possible is done by looking at the number of sign bits in the FFT input data.

11. The improvement of claim 10, wherein downscaling is done by shifting the FFT input data a given two bits to the right.

12. The improvement of claim 11, wherein the FFT'"'"'s are implemented in 19-bit precision using fixed point 16-bit processing.