Circuit and method of generating a phase locked loop signal having an offset reference

• US 6,137,995 A
• Filed: 12/08/1998
• Issued: 10/24/2000
• Est. Priority Date: 12/08/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Durec, Jeffrey C., Lovelace, David Kevin
• Primary Examiner(s): Nguyen, Lee
• Assistant Examiner(s): Nguyen, Simon
• Application Number:
  US09/207,869
• Time in Patent Office: 686 Days
• Field of Search: 455/75, 455/69, 455/85, 455/86, 455/88, 455/23, 455/24, 455/42, 455/47, 455/71, 455/73, 455/180.3, 455/109, 455/112, 455/165.1, 455/260
• US Class Current: 455/75
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03C 3/0975 applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

An integrated transceiver circuit (10) includes a single side-band mixer (12) and a phase locked loop (30). The phase locked loop (30) includes a phase detector (32) coupled to a voltage controlled oscillator (36) via a summing circuit (33) and a low pass filter (34). A feedback signal from the voltage controlled oscillator (36) is transferred to the phase detector (32) through a counter (38). Either a phase modulation signal or a frequency modulation signal are inputs of summing circuit (33) and modulate the transmitter carrier signal generated by the voltage controlled oscillator (36). The carrier signal generated at an output terminal (40) of the transmitter tracks the frequency of the local oscillator signal that is supplied at an input terminal of the single side-band mixer (12) in the receiver.

Claims

1. An integrated transceiver circuit, comprising:

a single side-band mixer in a receiver section of the integrated transceiver circuit having a first input coupled for receiving a first signal and a second input coupled for receiving a second signal; and

a phase lock loop in a transmitter section of the integrated transceiver circuit having an input coupled to an output of the single side-band mixer, wherein the phase lock loop supplies an output signal that has a frequency that differs from the first signal by a programmable offset frequency, wherein the phase lock loop further comprises;

a phase detector having a first input coupled to an output of the single side-band mixer;

a summing circuit having a first input coupled to an output of the phase detector and a second input coupled for receiving a third signal;

a low pass filter having an input coupled to an output of the summing circuit;

a controlled oscillator having an input coupled to an output of the low pass filter; and

a frequency dividing circuit having an input coupled to an output of the controlled oscillator and an output coupled to a second input of the phase detector.

2. An integrated transceiver circuit, comprising:

a single side-band mixer in a receiver section of the integrated transceiver circuit having a first input coupled for receiving a first signal and a second input coupled for receiving a second signal; and

a phase lock loop in a transmitter section of the integrated transceiver circuit having an input coupled to an output of the single side-band mixer, wherein the phase lock loop supplies an output signal that has a frequency that differs from the first signal by a programmable offset frequency, wherein the phase lock loop comprises;

a phase detector having a first input coupled to an output of the single side-band mixer;

a summing circuit having a first input coupled to an output of the phase detector and a second input coupled for receiving a phase modulation signal;

a low pass filter having an input coupled to an output of the summing circuit;

a controlled oscillator having an input coupled to an output of the low pass filter; and

a frequency dividing circuit having an input coupled to an output of the controlled oscillator and an output coupled to a second input of the phase detector.

3. The integrated transceiver circuit of claim 2, wherein the phase modulation signal is generated by an integrator whose input is a frequency modulation signal.

4. An integrated transceiver circuit, comprising:

a single side-band mixer having a first input coupled for receiving a first signal and a second input coupled for receiving a second signal;

a phase detector having a first input coupled to an output of the single side-band mixer;

a summing circuit having a first input coupled to an output of the phase detector and a second input coupled for receiving a third signal;

a low pass filter having an input coupled to an output of the summing circuit;

a controlled oscillator having an input coupled to an output of the low pass filter; and

a frequency dividing circuit having an input coupled to an output of the controlled oscillator and an output coupled to a second input of the phase detector.

5. The integrated transceiver circuit of claim 4, wherein the second input of the summing circuit receives a phase modulation signal.

6. The integrated transceiver circuit of claim 5, wherein the phase modulation signal is generated by an integrator whose input is the frequency modulation signal.

7. The integrated transceiver circuit of claim 4, wherein the single side-band mixer comprises:

a first counter having an input for receiving the first signal and an output that supplies a first frequency divided signal; and

a second counter having an input for receiving the second signal and an output that supplies a second frequency divided signal.

8. The integrated transceiver circuit of claim 7, further comprising:

a first phase shifter having an input coupled to the output of the first counter;

a second phase shifter having an input coupled to the output of the second counter;

a first mixer having a first input coupled to an output of the first phase shifter and a second input coupled to an output of the second phase shifter;

a second mixer having a first input coupled to the input of the first phase shifter and a second input coupled to the input of the second phase shifter; and

a summing circuit having first and second inputs coupled to outputs of the respective first and second mixers.

9. A method of generating a transmitter carrier signal that tracks a frequency of a local oscillator signal in a receiver, comprising the steps of:

generating an output signal having a frequency that is a difference in frequencies of a signal and the local oscillator signal; and

generating a modulated transmitter signal locked in frequency to the output signal, wherein the modulated transmitter signal is offset in frequency with respect to the local oscillator signal, wherein the step of generating an output signal further comprises the step of generating a first divided signal from the signal and a second divided signal from the local oscillator signal.

10. The method of claim 9, further comprising the steps of generating first and second quadrature components from the first and second divided signals, respectively.

11. The method of claim 10, further comprising the step of mixing the first and second quadrature components to generate first sum and difference signals.

12. The method of claim 10, further comprising the step of mixing the first and second divided signals to generate second sum and difference signals.

13. The method of claim 12, further comprising the step of summing the first and second sum and difference signals to generate the output signal.

14. The method of claim 12, further comprising the step of providing a difference of the first and second sum and difference signals to generate the output signal.

15. The method of claim 12, further comprising the step of alternating between providing a summed output and a difference output of the first and second sum and difference signals to generate a modulated output signal.

16. A transceiver circuit, comprising:

a single side-band mixer having a first input coupled for receiving a first signal and a second input coupled for receiving a second signal; and

a phase lock loop having an input coupled to an output of the single side-band mixer and an output for providing an output signal that has a frequency that differs from the first signal by a programmable offset frequency;

wherein the single side-band mixer comprises;

a first counter having an input for receiving the first signal and an output that supplies a first frequency divided signal; and

a second counter having an input for receiving the second signal and an output that supplies a second frequency divided signal.