Multiple level cache memory with overlapped L1 and L2 memory access

• US 6,138,208 A
• Filed: 04/13/1998
• Issued: 10/24/2000
• Est. Priority Date: 04/13/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hofstee, Harm Peter, Meltzer, David, Dhong, Sang Hoo, Silberman, Joel Abraham
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/059,000
• Time in Patent Office: 925 Days
• Field of Search: 711/3, 711/117, 711/118, 711/119, 711/120, 711/122, 711/123, 711/125, 711/126, 711/150, 711/138
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0884 Parallel mode, e.g. in parallel with main memory or CPU
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.

Claims

1. A method of providing data from a cache to a processor of a computer system, comprising the steps of:

loading a value into a lower level of the cache;

issuing a request from the processor that the value be supplied by a higher level of the cache;

in response to said issuing step, determining that a cache miss of the value has occurred at the higher level of the cache;

forwarding the request to the lower level of the cache during said determining step, including the step of decoding an address related to a particular location of the value in a system memory device of the computer system; and

in response to said determining step, supplying the value from the lower level of the cache.

2. The method of claim 1 wherein the value is supplied from the lower level of the cache directly to the processor.

3. The method of claim 1 wherein said decoding step includes the step of operating a plurality of decoders in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests.

4. The method of claim 1 wherein said supplying step includes the step of gating the address to a plurality of memory array word line drivers of the lower level of the cache.

5. The method of claim 1 wherein said decoding step includes the step of immediately decoding a plurality of bits of the address that do not require virtual-to-real translation.

6. The method of claim 5 wherein said decoding step includes the step of translating another plurality of bits of the address prior to completion of said determining step.

7. A cache for providing values to a processor of a computer system, the cache comprising:

a higher cache level;

a lower cache level; and

means for reducing memory access latency when a cache miss of a value has occurred at said higher cache level and the value is supplied from said lower cache level, said reducing means providing an overlap of a first access of said higher cache level and a second access of said lower cache level, by forwarding a request of the value from the processor to said lower cache level while said first cache level determines whether a cache miss has occurred, the request being forwarded by decoding an address related to a particular location of the value in a system memory device of the computer system.

8. The cache of claim 7 wherein:

said higher cache level is a first cache level connected to the processor; and

said lower cache level is a second cache level connected to said first cache level.

9. The cache of claim 7 wherein said second cache level is further connected to a third cache level.

10. The cache of claim 7 wherein said means for reducing said memory access latency supplies the value from said lower cache level directly to the processor.

11. The cache of claim 8 wherein reducing means supplies the value by gating the address to a plurality of memory array word line drivers of said lower cache level.