Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line

• US 6,138,213 A
• Filed: 06/27/1997
• Issued: 10/24/2000
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: McMinn, Brian D.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US08/884,434
• Time in Patent Office: 1,215 Days
• Field of Search: 711/3, 711/118, 711/123, 711/136, 711/137, 711/147, 711/154, 711/155, 711/207, 712/207, 712/237
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache

Abstract

A cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests initiated by a microprocessor connected to the cache are stored into the non-prefetch ways. Accessed cache lines are thereby maintained within the cache separately from prefetch cache lines. When a prefetch cache line is presented to the cache for storage, the prefetch cache line may displace another prefetch cache line but does not displace an accessed cache line. A cache hit in either the prefetch way or the non-prefetch ways causes the cache line to be delivered to the requesting microprocessor in a cache hit fashion. The cache is further configured to move prefetch cache lines from the prefetch way to the non-prefetch way if the prefetch cache lines are requested (i.e. they become accessed cache lines). Instruction cache lines may be moved immediately upon access, while data cache line accesses may be counted and a number of accesses greater than a predetermined threshold value may occur prior to moving the data cache line from the prefetch way to the non-prefetch way. Additionally, movement of an accessed cache line from the prefetch way to the non-prefetch way may be delayed until the accessed cache line is to be replaced by a prefetch cache line.

Claims

1. A cache comprising:

a storage including at least a first way for storing cache lines and at least one prefetch way for storing prefetch cache lines, said storage comprising a plurality of rows selectable by an index portion of an address input to said cache, wherein said first way includes a first plurality of cache line storage locations, and wherein each of said first plurality of cache line storage locations is included within a respective one of said plurality of rows, and wherein said prefetch way includes a second plurality of cache line storage locations, and wherein each of said second plurality of cache line storage locations is included within said respective one of said plurality of rows; and

a control unit coupled to said storage, wherein said control unit is configured to store a first prefetch cache line into said prefetch way, and wherein said control unit is further configured to move said first prefetch cache line from said prefetch way into said first way if said prefetch cache line is requested from said cache, and wherein said first prefetch cache line includes a referenced indication, and wherein said control unit is configured to place said reference indication into a first state if said first prefetch cache line is requested from said cached, and wherein said first state is indicative of said first prefetch cache line being requested, and wherein said referenced indication is indicative, in second state, that said first prefetch cache line has not been requested from said cache.

2. The cache as recited in claim 1 wherein said control unit is configured to initialize said referenced indication to said second state upon storing said first prefetch cache line into said prefetch way.

3. The cache as recited in claim 1 further comprising a prefetch control unit coupled to said control unit, wherein said prefetch control unit is configured to prefetch cache lines into said cache.

4. The cache as recited in claim 3 wherein said control unit is configured to delay moving said first prefetch cache line into said first way until said prefetch control unit provides a second prefetch cache line for storing in said prefetch way.

5. The cache as recited in claim 4 wherein said second prefetch cache line replaces said first prefetch cache line within said prefetch way.

6. The cache as recited in claim 5 wherein said control unit is configured to move said first prefetch cache line into said first way responsive to said referenced indication being in said first state and said second prefetch cache line replacing said first prefetch cache line within said prefetch way.

7. The cache as recited in claim 1 wherein said first prefetch cache line comprises a data to be operated upon in response to an execution of instructions.

8. The cache as recited in claim 7 wherein said first prefetch cache line includes a counter, and wherein said control unit is configured to increment said counter upon request of said first prefetch cache line from said cache.

9. The cache as recited in claim 8 wherein said control unit is configured to place said referenced indication into said first state if said counter equals or exceeds a threshold value.

10. The cache as recited in claim 9 further comprising a prefetch control unit coupled to said control unit, wherein said prefetch control unit is configured to prefetch cache lines into said cache, and wherein said control unit is configured to delay moving said first prefetch cache line into said first way until said prefetch control unit provides a second prefetch cache line for storing in said prefetch way, and wherein said second prefetch cache line replaces said first prefetch cache line within said prefetch way, and wherein said control unit is configured to move said first prefetch cache line into said first way responsive to said referenced indication being in said first state and said second prefetch cache line replacing said first prefetch cache line within said prefetch way.

11. The cache as recited in claim 1 wherein said storage includes a plurality of ways including said first way for storing cache lines.

12. The cache as recited in claim 11 wherein said first way stores a least recently used cache line of a plurality of cache lines stored in cache line storage locations within a first row of said plurality of rows, said first row also including a first one of said second plurality of cache line storage location storing said first prefetch cache line.

13. A method for prefetching data in a computer system, comprising:

storing a first prefetched cache line into a prefetch way of a cache having at least a first way in addition to said prefetch way, said prefetch way used to store only prefetched cache lines, said cache comprising a plurality of rows selectable by an index portion of an address input to said cache, wherein said first way includes a first plurality of cache line storage locations, and wherein each of said first plurality of cache line storage locations is included within a respective one of said plurality of rows, and wherein said prefetch way includes a second plurality of cache line storage locations, and wherein each of said second plurality of cache line storage locations is included within said respective one of said plurality of rows; and

moving said first prefetched cache line from said prefetch way into said first way if a request for said first prefetched cache line is received in said cache, wherein said moving comprises placing a referenced indication corresponding to said first prefetched cache line into a first state indicating that said receiving a request has occurred, and wherein said reference indication is indicative, in a second state, that said first prefetch cache line has not been requested from said cache.

14. The method as recited in claim 13 wherein said moving further comprises transferring said first prefetched cache line into said first way upon storing a second prefetched cache line into said prefetch way, said second prefetched cache line replacing said first prefetched cache line within said prefetch way.

15. The method as recited in claim 14 wherein said transferring is responsive to said referenced indication being in said first state.

16. The method as recited in claim 13 wherein said moving comprises incrementing a counter corresponding to said first prefetched cache line upon said receiving a request.

17. The method as recited in claim 16 wherein said placing a referenced indication corresponding to said first prefetched cache line into a first state is performed in response to said counter equaling or exceeding a threshold value.

18. The method as recited in claim 17 further comprising transferring said first prefetched cache line into said first way responsive to said referenced indication being in said first state and a second prefetch cache line replacing said first prefetched cache line within said prefetch way.

19. A computer system comprising:

a microprocessor; and

a cache coupled to said microprocessor, said cache including a prefetch way and at least a first way, said cache comprising a plurality of rows selectable by an index portion of an address input to said cache, wherein said first way includes a first plurality of cache line storage locations, and wherein each of said first plurality of cache line storage locations is included within a respective one of said plurality of rows, and wherein said prefetch way includes a second plurality of cache line storage locations, and wherein each of said second plurality of cache line storage locations is included within said respective one of said plurality of rows, wherein said cache is configured to store a prefetched cache line into said prefetch way, and wherein said cache is configured to move said prefetched cache line from said prefetch way into said first way if said microprocessor accesses said prefetched cache line within said prefetch way, and wherein said first prefetch cache line includes a referenced indication, and wherein said control unit is configured to place said referenced indication into a first state if said first prefetch cache line is requested from said cache, and wherein said first state is indicative of said first prefetch cache line being requested, and wherein said referenced indication is indicative, in a second state, that said first prefetch cache line has not been requested from said cache.

20. The computer system as recited in claim 19 wherein said cache is configured to delay moving said prefetched cache line into said first way until a subsequent occurrence of a predetermined event.