Device for the jump-like addressing of specific lines of a serially operating digital memory

• US 6,138,227 A
• Filed: 03/13/1998
• Issued: 10/24/2000
• Est. Priority Date: 09/13/1995
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Schmitt-Landsiedel, Doris, Thewes, Roland, Bollu, Michael, von Basse, Paul-Werner
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US09/043,046
• Time in Patent Office: 956 Days
• Field of Search: 711/109, 711/110, 711/218, 711/217, 711/213, 365/189.12, 365/73, 365/78, 365/240
• US Class Current: 711/213
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.

Claims

1. A device for jump-like addressing of specific lines of a serially operating digital memory, comprising:

two control devices which are jointly assigned to the specific lines, wherein each of said two control devices has a plurality of outputs and, at said outputs, chronologically successively generates a specific binary information item assigned to a respective one of said two control devices and decisive for addressing one of said specific lines,

a plurality of linking elements, each of said linking elements being assigned to one of said specific lines and having an output assigned to respective ones of said specific lines, said linking elements each having an input assigned to one of the two control devices as well as an input assigned to an other one of said two control devices,

each of said linking elements addressing the one of said specific lines assigned to that respective linking element alone via its output precisely when there is present at its input assigned to the one control device the specific binary information item assigned to that control device and, simultaneously, there is present at its input assigned to the other control device the specific binary information item assigned to the other control device,

the linking elements being subdivided into groups which do not share the same elements and in each case have a plurality of linking elements, the groups together yielding all the linking elements inputs, assigned to the one of the two control devices, of the linking elements being connected to the outputs of the corresponding control device in such a way that each of said outputs is connected to only one of said inputs of each of said groups and

inputs, assigned to the other control device, of the linking elements being connected in groups to the outputs of the other control device in such a way that the inputs of each of said groups are jointly connected to one of the outputs assigned to this group alone.

2. A device according to claim 1, wherein at least one of said two control devices includes a control chain in which an associated binary information item appears chronologically successively in a specific direction at the outputs of that control device.

3. A method for jump-like addressing of specific lines, in a device as claimed in claim 1, comprising the steps of:

generating successively specific binary information item assigned to one control device at outputs of that control device,

maintaining at each of said outputs the generated specific binary information item for a specific period, and

generating successively during said specific period the specific binary information item assigned to an other control device at all outputs of the other control device.