Reduction of masking and doping steps in a method of fabricating a liquid crystal display
First Claim
1. A method of fabricating a liquid crystal display, comprising the steps of:
- providing an insulated substrate;
forming a common semiconductive layer defining a source region, an off-set region, a channel region, a drain region and a first storage electrode on the insulated substrate;
doping said source region, said drain region and said first storage electrode with impurities selectively and heavily;
forming a gate electrode on said channel region and a second storage electrode on said first storage electrode wherein said gate electrode has a gate insulating layer disposed thereunder and said second storage electrode has a storage capacitor insulating layer disposed thereunder;
forming an insulating interlayer covering an exposed surface of said insulated substrate including said gate electrode and said first storage electrode;
forming contact holes exposing each of said source region and said drain region;
forming a source wire connected to said source region and a drain wire connected to said drain region;
forming a passivation layer covering an exposed surface of said substrate which includes covering said source wire and said drain wire;
forming a contact hole exposing said drain wire; and
forming a pixel electrode connected to said drain wire.
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Accused Products
Abstract
A method of fabricating a liquid crystal display includes the steps of forming a semiconductive layer with doped regions defining source regions, offset regions, channel regions, drain regions and first storage electrodes in an insulated substrate, simultaneously doping source and drain regions while doping the first storage electrodes with impurities selectively and heavily, forming a gate electrode on the channel region and a second storage electrode on the first storage electrode wherein the gate electrode has a gate insulating layer disposed thereunder and the second storage electrode has a storage capacitor insulating layer disposed thereunder, forming an insulating interlayer covering an exposed surface of the substrate which includes the gate electrode and the first storage electrode, forming contact holes exposing each of the source region and the drain region, forming a source wire connected to the source region and a drain wire connected to the drain region, forming a passivation layer covering an exposed surface of the substrate which includes the source wire and the drain wire, forming a contact hole exposing the drain wire, and forming a pixel electrode connected to the drain wire.
27 Citations
24 Claims
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1. A method of fabricating a liquid crystal display, comprising the steps of:
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providing an insulated substrate; forming a common semiconductive layer defining a source region, an off-set region, a channel region, a drain region and a first storage electrode on the insulated substrate; doping said source region, said drain region and said first storage electrode with impurities selectively and heavily; forming a gate electrode on said channel region and a second storage electrode on said first storage electrode wherein said gate electrode has a gate insulating layer disposed thereunder and said second storage electrode has a storage capacitor insulating layer disposed thereunder; forming an insulating interlayer covering an exposed surface of said insulated substrate including said gate electrode and said first storage electrode; forming contact holes exposing each of said source region and said drain region; forming a source wire connected to said source region and a drain wire connected to said drain region; forming a passivation layer covering an exposed surface of said substrate which includes covering said source wire and said drain wire; forming a contact hole exposing said drain wire; and forming a pixel electrode connected to said drain wire. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of fabricating a liquid crystal display including a pixel array which has a TFT and a storage capacitor and a circuit which has a CMOS device including a first type TFT and a second type TFT, said pixel array and said circuit formed in a common substrate, said method comprising the steps of:
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forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer on said substrate from a common semiconductor layer, wherein a source region, an off-set region, a channel region, a drain region and a first storage electrode of said TFT in said pixel array are defined in said first semiconductor layer, a source region, a channel region and a drain region of said first type TFT in said circuit are defined in said second semiconductor layer, and a source region, a channel region and a drain region of said second type TFT in said circuit are defined in said third semiconductor layer; doping heavily and selectively said source region, drain region and said first storage electrode in said first semiconductor layer and said source region and said drain region in said second semiconductor layer with first type impurities; forming a gate electrode on said channel region of said first semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder, a gate electrode on said channel region of said second semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder, a gate electrode on said channel region of said third semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder and a second storage electrode on said first storage electrode wherein said second storage electrode has a storage capacitor insulating layer disposed thereunder; doping said source and said drain region of said third semiconductor layer heavily and selectively with second type impurities; forming an insulating interlayer covering an exposed surface of said substrate, said exposed surface including said gate electrodes and said first storage electrode; forming contact holes exposing said source regions and said drain regions, respectively; forming a source wire connected to said source region of said first semiconductor layer, a drain wire connected to said drain region of said first semiconductor layer and a first wire, a second wire and a third wire which connect said source region and said drain region of said second semiconductor layer to said source region and said drain region of said third semiconductor layer to define said CMOS device including said first type TFT and said second type TFT; forming a passivation layer covering a surface of said substrate which includes covering said source wire, said drain wire, said first wire, said second wire and said third wire; forming a contact hole exposing said drain wire; and forming a pixel electrode connected to said drain wire. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of fabricating a liquid crystal display, said liquid crystal display including a pixel array which has a TFT and a storage capacitor and a circuit which has a CMOS device including a first type TFT and a second type TFT, said pixel array and said circuit formed in a common substrate, said method comprising the steps of:
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forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer from a common semiconductor layer on said substrate, wherein a source region, a channel region, a drain region and a first storage electrode of said TFT in said pixel array are defined in said first semiconductor layer, wherein a source region, a channel region and a drain region of said first type TFT in said circuit are defined in said second semiconductor layer, and a source region, a channel region and a drain region of said second type TFT in said circuit are defined in said third semiconductor layer; doping heavily and selectively said first storage electrode in said first semiconductor layer and said source region and said drain region in said second semiconductor layer with first typed impurities; forming a gate electrode on said channel region of said first semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder, a gate electrode on said channel region of said second semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder, a gate electrode on said channel region of said third semiconductor layer wherein said gate electrode has a gate insulating layer disposed thereunder and a second storage electrode on said first storage electrode wherein said second storage electrode has a storage capacitor insulating layer disposed thereunder; doping said source region and said drain region of said first semiconductor layer and said source region and said drain region of said third semiconductor layer heavily and selectively with second type impurities; forming an insulating interlayer covering an exposed surface of said substrate, said exposed surface including said gate electrodes and said first storage electrode; forming contact holes exposing said source regions and said drain regions, respectively; forming a source wire connected to said source region of said first semiconductor layer, a drain wire connecting said drain region of said first semiconductor layer to said first storage electrode and a first wire, a second wire and a third wire which connect said source region and said drain region of said second semiconductor layer to said source region and said drain region of said third semiconductor layer to define said CMOS device including said first type TFT and said second type TFT; forming a passivation layer covering a surface of said substrate which includes covering said source wire, said drain wire, said first, said second and said third wire; forming a contact hole exposing said drain wire; and forming a pixel electrode connected to said drain wire. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification