Method of making spiral-type RF inductors having a high quality factor (Q)

• US 6,140,197 A
• Filed: 08/30/1999
• Issued: 10/31/2000
• Est. Priority Date: 08/30/1999
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), National University of Singapore
• Inventors: Chu, Shau-Fu Sanford, Chew, Kok Wai Johnny, Cha, Cher Liang, Chua, Chee Tee
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/385,525
• Time in Patent Office: 428 Days
• Field of Search: 438/381, 438/421, 257/531
• US Class Current: 438/381
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the dielectric layer. The intermetal dielectric layer is patterned whereby a plurality of openings are made through the intermetal dielectric layer to the semiconductor substrate. Thereafter, an oxide layer is deposited overlying the intermetal dielectric layer and capping the plurality of openings thereby forming air gaps within the intermetal dielectric layer. A metal plug is formed through the oxide layer and the intermetal dielectric layer to the metal line. A metal layer is deposited overlying the oxide layer and patterned to form an inductor wherein a portion of the inductor contacts the metal line through the metal plug to complete formation of an inductor utilizing air as an underlying barrier in the fabrication of an integrated circuit.

Claims

1. A method of fabricating an inductor in the fabrication of an integrated circuit comprising:

providing a metal line overlying a dielectric layer on a semiconductor substrate;

depositing an intermetal dielectric layer overlying said metal line and said dielectric layer;

patterning said intermetal dielectric layer whereby a plurality of openings are made through said intermetal dielectric layer to said dielectric layer;

thereafter depositing an oxide layer overlying said intermetal dielectric layer and capping said plurality of openings thereby forming air gaps within said intermetal dielectric layer;

forming a metal plug through said oxide layer and said intermetal dielectric layer to said metal line; and

depositing a metal layer overlying said oxide layer and patterning said metal layer to form a spiral-shaped inductor wherein a portion of said inductor contacts said metal line through said metal plug to complete formation of said inductor in the fabrication of said integrated circuit.

2. The method according to claim 1 wherein said metal line comprises aluminum copper having an underlying titanium nitride barrier layer and an overlying titanium nitride anti-reflective coating layer having a combined thickness of between about 5400 and 6600 Angstroms.

3. The method according to claim 1 wherein said air gaps each have a depth of between about 6000 and 40,000 Angstroms.

4. The method according to claim 1 wherein said air gaps each have a width of between about 0.40 and 0.52 microns.

5. The method according to claim 1 wherein said intermetal dielectric layer comprises tetraethoxysilane (TEOS) oxide having a thickness of between about 16,500 and 19,500 Angstroms.

6. The method according to claim 1 wherein said steps of depositing said intermetal dielectric layer and patterning said intermetal dielectric layer to form openings are repeated whereby said openings have a depth equal to the combined thickness of said intermetal dielectric layers.

7. The method according to claim 1 wherein said oxide layer is deposited to a thickness of between about 1000 and 1500 Angstroms.

8. The method according to claim 1 wherein said metal plug comprises tungsten.

9. The method according to claim 1 wherein said metal layer comprises aluminum copper having an underlying titanium nitride barrier layer and an overlying titanium nitride anti-reflective coating layer having a combined thickness of between about 8100 and 9900 Angstroms.

16. The method according to claim 1 wherein said metal layer is deposited to a thickness of between about 8100 and 9900 Angstroms.

10. A method of fabricating an inductor in the fabrication of an integrated circuit comprising:

providing a metal line overlying a dielectric layer on a semiconductor substrate;

depositing an intermetal dielectric layer overlying said metal line and said semiconductor substrate;

patterning said intermetal dielectric layer whereby a plurality of openings are made through said intermetal dielectric layer to said dielectric layer;

thereafter depositing an oxide layer overlying said intermetal dielectric layer and capping said plurality of openings thereby forming air gaps within said intermetal dielectric layer;

forming a tungsten plug through said oxide layer and said intermetal dielectric layer to said metal line; and

depositing a metal layer overlying said oxide layer and patterning said metal layer to form a spiral-shaped inductor wherein a portion of said inductor contacts said metal line through said tungsten plug to complete formation of said inductor in the fabrication of said integrated circuit.

11. The method according to claim 10 wherein said metal line has a thickness of between about 5400 and 6600 Angstroms.

12. The method according to claim 10 wherein said air gaps each have a depth of between about 0.6 and 40.0 microns and a width of between about 0.4 and 0.52 microns.

13. The method according to claim 10 wherein said intermetal dielectric layer comprises tetraethoxysilane (TEOS) oxide having a thickness of between about 16,500 and 19,500 Angstroms.

14. The method according to claim 10 wherein said steps of depositing said intermetal dielectric layer and patterning said intermetal dielectric layer to form openings are repeated whereby said openings have a depth equal to the combined thickness of said intermetal dielectric layers.

15. The method according to claim 10 wherein said oxide layer is deposited to a thickness of between about 1000 and 1500 Angstroms.

17. A method of fabricating an inductor in the fabrication of an integrated circuit comprising:

providing a metal line overlying a dielectric layer on a semiconductor substrate;

depositing an intermetal dielectric layer overlying said metal line and said dielectric layer;

patterning said intermetal dielectric layer whereby a plurality of openings are made through said intermetal dielectric layer to said dielectric layer;

thereafter repeating said steps of depositing said intermetal dielectric layer and patterning said intermetal dielectric layer to form openings until said openings have a depth of between 0.6 and 40.0 microns;

thereafter depositing an oxide layer overlying said intermetal dielectric layer and capping said plurality of openings thereby forming air gaps within said intermetal dielectric layer wherein said air gaps each have a width of 0.40 to 0.52 microns and a depth of 0.6 to 40.0 microns;

forming a tungsten plug through said oxide layer and said intermetal dielectric layer to said metal line; and

depositing a metal layer overlying said oxide layer and patterning said metal layer to form a spiral-shaped inductor wherein a portion of said inductor contacts said metal line through said tungsten plug to complete formation of said inductor in the fabrication of said integrated circuit.

18. The method according to claim 17 wherein said intermetal dielectric layer comprises tetraethoxysilane (TEOS) oxide having a thickness of between about 16,500 and 19,500 Angstroms.

19. The method according to claim 17 wherein said oxide layer is deposited to a thickness of between about 1000 and 1500 Angstroms.