Robust diffusion barrier for Cu metallization
First Claim
1. A method of copper metallization in the fabrication of an integrated circuit device comprising:
- providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization;
covering said semiconductor device structures with an insulating layer;
opening a via through said insulating layer to one of said underlying semiconductor device structures;
conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta2 N and wherein grain boundaries of said TaN layer and said Ta2 N layer are misaligned; and
depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device.
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Abstract
A new method of forming a stacked tantalum nitride barrier layer to prevent copper diffusion is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A via is opened through the insulating layer to one of the underlying semiconductor device structures. A stacked mode tantalum nitride barrier layer is conformally deposited within the via. A layer of copper is deposited overlying the stacked mode tantalum nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device. The stacked mode tantalum nitride barrier layer has misaligned grain boundaries. This prevents diffusion of copper into the dielectric layer.
29 Citations
16 Claims
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1. A method of copper metallization in the fabrication of an integrated circuit device comprising:
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providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization; covering said semiconductor device structures with an insulating layer; opening a via through said insulating layer to one of said underlying semiconductor device structures; conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta2 N and wherein grain boundaries of said TaN layer and said Ta2 N layer are misaligned; and depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 14)
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8. A method of copper metallization in the fabrication of an integrated circuit device comprising:
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providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization; covering said semiconductor device structures with an insulating layer; opening a via through said insulating layer to one of said underlying semiconductor device structures; conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta2 N wherein said TaN layer has a face-centered cubic structure and wherein said Ta2 N layer has a hexagonal closed package structure and wherein grain boundaries of said TaN layer and said Ta2 N layer are misaligned; and depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device. - View Dependent Claims (9, 10, 11, 12, 15)
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13. A method of copper metallization in the fabrication of an integrated circuit device comprising:
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providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization; covering said semiconductor device structures with an insulating layer; opening a via through said insulating layer to one of said underlying semiconductor device structures; depositing a tantalum layer within said via; conformally depositing a stacked mode tantalum nitride barrier layer within said via overlying said tantalum layer wherein said stacked mode tantalum nitride barrier layer comprises a layer of TaN overlying a layer of Ta2 N wherein said TaN layer has a face-centered cubic structure and wherein said Ta2 N layer has an amorphous structure and wherein the grain boundaries of said TaN and said Ta2 N layers are misaligned; and depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer wherein said misaligned grain boundaries prevents said copper from diffusing through said stacked mode tantalum nitride barrier layer into said insulating layer to complete said copper metallization in the fabrication of said integrated circuit device. - View Dependent Claims (16)
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Specification