Robust diffusion barrier for Cu metallization

• US 6,140,231 A
• Filed: 02/12/1999
• Issued: 10/31/2000
• Est. Priority Date: 02/12/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chung-Shi, Shu, Shau-Lin, Yu, Chen-Hua
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/249,257
• Time in Patent Office: 627 Days
• Field of Search: 438/627, 438/628, 438/687, 438/643, 438/653, 438/651, 438/655, 438/657, 438/672, 438/675, 438/644, 451/57
• US Class Current: 438/653
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations

Abstract

A new method of forming a stacked tantalum nitride barrier layer to prevent copper diffusion is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A via is opened through the insulating layer to one of the underlying semiconductor device structures. A stacked mode tantalum nitride barrier layer is conformally deposited within the via. A layer of copper is deposited overlying the stacked mode tantalum nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device. The stacked mode tantalum nitride barrier layer has misaligned grain boundaries. This prevents diffusion of copper into the dielectric layer.

Claims

1. A method of copper metallization in the fabrication of an integrated circuit device comprising:

providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization;

covering said semiconductor device structures with an insulating layer;

opening a via through said insulating layer to one of said underlying semiconductor device structures;

conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta₂ N and wherein grain boundaries of said TaN layer and said Ta₂ N layer are misaligned; and

depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device.

2. The method according to claim 1 further comprising depositing a tantalum layer underlying said stacked mode tantalum nitride barrier layer.

3. The method according to claim 1 wherein said step of depositing said stacked mode tantalum nitride barrier layer comprises:

depositing a first layer of TaN within said via opening; and

depositing a second layer of Ta₂ N overlying said TaN layer.

4. The method according to claim 1 wherein said step of depositing said stacked mode tantalum nitride barrier layer comprises:

depositing a first layer of Ta₂ N within said via opening; and

depositing a second layer of TaN overlying said Ta₂ N layer.

5. The method according to claim 1 wherein said TaN layer has a face-centered cubic structure and wherein said Ta₂ N layer has a hexagonal closed package structure.

6. The method according to claim 1 wherein said TaN layer has a face-centered cubic structure and wherein said Ta₂ N layer has an amorphous structure.

7. The method according to claim 1 wherein said stacked mode tantalum nitride barrier layer prevents copper diffusion into said insulating layer.

14. The method according to claim 1 wherein said TaN layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 15 and 20 sccm and wherein said Ta₂ N layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 10 and 25 sccm.

8. A method of copper metallization in the fabrication of an integrated circuit device comprising:

providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization;

covering said semiconductor device structures with an insulating layer;

opening a via through said insulating layer to one of said underlying semiconductor device structures;

conformally depositing a stacked mode tantalum nitride barrier layer within said via wherein said stacked mode tantalum nitride barrier layer comprises a first layer of TaN and a second layer of Ta₂ N wherein said TaN layer has a face-centered cubic structure and wherein said Ta₂ N layer has a hexagonal closed package structure and wherein grain boundaries of said TaN layer and said Ta₂ N layer are misaligned; and

depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer to complete said copper metallization in the fabrication of said integrated circuit device.

9. The method according to claim 8 further comprising depositing a tantalum layer underlying said stacked mode tantalum nitride barrier layer.

10. The method according to claim 8 wherein said step of depositing said stacked mode tantalum nitride barrier layer comprises:

depositing a first layer of TaN within said via opening; and

depositing a second layer of Ta₂ N overlying said TaN layer.

11. The method according to claim 8 wherein said step of depositing said stacked mode tantalum nitride barrier layer comprises:

depositing a first layer of Ta₂ N within said via opening; and

depositing a second layer of TaN overlying said Ta₂ N layer.

12. The method according to claim 8 wherein said stacked mode tantalum nitride barrier layer prevents copper diffusion into said insulating layer.

15. The method according to claim 8 wherein said TaN layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 15 and 20 sccm and wherein said Ta₂ N layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 10 and 25 sccm.

13. A method of copper metallization in the fabrication of an integrated circuit device comprising:

providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include silicided gate electrodes and associated silicided source and drain regions and lower level metallization;

covering said semiconductor device structures with an insulating layer;

opening a via through said insulating layer to one of said underlying semiconductor device structures;

depositing a tantalum layer within said via;

conformally depositing a stacked mode tantalum nitride barrier layer within said via overlying said tantalum layer wherein said stacked mode tantalum nitride barrier layer comprises a layer of TaN overlying a layer of Ta₂ N wherein said TaN layer has a face-centered cubic structure and wherein said Ta₂ N layer has an amorphous structure and wherein the grain boundaries of said TaN and said Ta₂ N layers are misaligned; and

depositing a layer of copper overlying said stacked mode tantalum nitride barrier layer wherein said misaligned grain boundaries prevents said copper from diffusing through said stacked mode tantalum nitride barrier layer into said insulating layer to complete said copper metallization in the fabrication of said integrated circuit device.

16. The method according to claim 13 wherein said TaN layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 15 and 20 sccm and wherein said Ta₂ N layer is formed by reactive ion sputtering using a tantalum target and N₂ gas flowed at between about 10 and 25 sccm.