Digital phase detector and charge pump system reset and balanced current source matching

• US 6,140,853 A
• Filed: 06/24/1999
• Issued: 10/31/2000
• Est. Priority Date: 11/29/1996
• Status: Expired due to Term

• Current Assignee: PLL Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lo, Chung-Wen Dennis
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/339,435
• Time in Patent Office: 495 Days
• Field of Search: 327/157, 327/3, 327/7, 327/5, 327/142, 327/146, 327/147, 327/156, 331/17, 331/1 A
• US Class Current: 327/157
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Claims

1. A circuit comprising:

a charge pump circuit configured to present a first output and a second output in response to a first phase comparator output signal and a second phase comparator output signal;

a phase comparator circuit configured to provide said first and second phase comparator output signals in response to (i) a first input phase signal, (ii) a second input phase signal, and (iii) a reset signal; and

a logic circuit configured to present said reset signal in response to said first and second outputs, and said first and second phase comparator output signals.

2. The circuit according to claim 1, wherein said logic circuit further comprises:

a current source;

a first current mirror connected to said current source; and

a second current mirror connected to said current source, wherein one of said first and second current mirrors is active in response to said first and second outputs.

3. The circuit according to claim 2, wherein said first current mirror comprises one or more p-channel transistors.

4. The circuit according to claim 2, wherein said second current mirror comprises one or more n-channel transistors.

5. The circuit according to claim 2, wherein said first current mirror is connected in series with said current source and said second current mirror is connected in series with said current source.

6. The circuit according to claim 1, wherein said phase comparator comprises:

a sourcing and a sinking current source connected at a common node; and

a filter capacitor connected to said common node.

7. The circuit according to claim 6, wherein said first input phase signal comprises an input frequency signal and said second input phase signal comprises a reference signal configured to adjust said first and second phase comparator output signals.

8. The circuit according to claim 7, wherein:

said logic circuit is configured to present said reset signal to said phase comparator.

9. The circuit according to claim 8, wherein said logic circuit further comprises:

a discharging circuit and a charging circuit configured to combine a first logic output and a second logic output to produce said reset signal at said phase comparator, wherein said discharging circuit comprises (i) a first logic output node and (ii) a first logic input and said charging circuit comprises (i) a second logic output node and (ii) a second logic input.

10. The circuit according to claim 9, wherein said logic circuit comprises:

said first logic output node coupled to a first supply voltage through a first discharging switch, wherein said discharging circuit is configured to generate a first logic output at said first logic output node in response to said first output charge pump node, wherein said first discharging switch is controlled by said second output phase node; and

said second logic output node coupled to a second supply voltage through a second discharging switch, wherein said charging circuit is configured to generate a second logic output at said second logic output node in response to said second output charge pump node, wherein said second discharging switch is controlled by said first output phase node.

11. The circuit according to claim 10, wherein said discharging circuit includes (i) a first current source, (ii) a first sensing capacitor, and (iii) a first resistor.

12. The circuit according to claim 11, wherein said first current source is connected in parallel with said first resistor and said first sensing capacitor.

13. The circuit according to claim 10, wherein said charging circuit includes (i) a second current source, (ii) a second sensing capacitor (iii) and a second resistor.

14. The circuit according to claim 13, wherein said second current source is connected in parallel with said second resistor and said second sensing capacitor.

15. The circuit according to claim 12, wherein said first sensing capacitor discharges a function of said filter capacitor.

16. The circuit according to claim 14, wherein said second current source operates a function of said sinking current source.

17. The circuit according to claim 16, wherein said second sensing capacitor operates a function of said filter capacitor.