Phase lock loop enabling smooth loop bandwidth switching

• US 6,140,882 A
• Filed: 11/23/1998
• Issued: 10/31/2000
• Est. Priority Date: 11/23/1998
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Tropian, Inc. (Panasonic Holdings Corporation)
• Inventors: Sander, Brian
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Glenn, Kimberly E
• Application Number:
  US09/197,523
• Time in Patent Office: 708 Days
• Field of Search: 331/25, 331/105, 331/108, 327/105, 327/108
• US Class Current: 331/25
• CPC Class Codes: H03L 7/1972 for reducing the locking time interval H03L7/1974, H03L7/199 take precedence

Abstract

The present invention, generally speaking, provides a PLL that enables smooth switching of loop bandwidth without changing the loop filter. In accordance with one aspect of the invention, the loop bandwidth of a phase lock loop including an output frequency divider and a reference frequency divider is changed by changing a divisor of the output frequency divider by a factor and changing a divisor of the reference frequency divider by substantially the same factor. If the factor is greater than one, the loop bandwidth is decreased. If the factor is less than one, then the loop bandwidth is increased. In accordance with another aspect of the invention, a phase lock loop includes an oscillator having a control input, a phase comparator, a loop filter, and a feedback path including an output frequency divider. A reference frequency divider is also provided. A controller is coupled to the output frequency divider and to the reference frequency divider for changing a divisor of each at substantially the same time in response to a bandwidth select signal. The controller changes the divisors by substantially the same factor, changing the loop bandwidth without affecting the output frequency of the phase lock loop.

Claims

1. A method of changing the loop bandwidth of a phase lock loop including an output frequency divider and a reference frequency divider, comprising:

designing the phase lock loop such that a phase margin of greater than 50°

exists throughout at least a 10;

1 frequency offset range;

changing a divisor of the output frequency divider by a factor α

; and

changing a divisor of the reference frequency divider by substantially the same factor;

whereby a smooth change is effected in the loop bandwidth in a single step without substantially impairing phase margin of the phase lock loop.

2. The method of claim 1, wherein α

is greater than one, decreasing the loop bandwidth.

3. The method of claim 1, wherein α

is less than one, increasing the loop bandwidth.

4. A phase lock loop comprising:

an oscillator having a control input;

a phase comparator;

a loop filter coupled to the phase comparator and to the oscillator;

a feedback loop coupled from an output signal of the oscillator to an input signal of the phase comparator, the feedback loop including an output frequency divider; and

a reference frequency divider having an input coupled to a reference frequency signal and an output coupled to the phase comparator; and

a controller coupled to the output frequency divider and to the reference frequency divider for changing a divisor of the output frequency divider and a divisor of the reference frequency divider at substantially the same time in response to a bandwidth select signal;

wherein the phase lock loop is designed such that a phase margin of greater than 50°

exists throughout at least a 10;

1 frequency offset range; and

wherein changing a divisor of the output frequency divider and a divisor of the reference frequency divider at substantially the same time effects a smooth change in the loop bandwidth in a single step without substantially impairing phase margin of the phase lock loop.

5. The apparatus of claim 4, wherein the controller changes a divisor of the output frequency divider and a divisor of the reference frequency divider by substantially the same factor.

6. The apparatus of claim 5, wherein said factor is greater than one, decreasing the loop bandwidth.

7. The apparatus of claim 5, wherein said factor is less than one, increasing the loop bandwidth.