Display system having multiple memory elements per pixel with improved layout design
DCFirst Claim
Patent Images
1. A display matrix comprising:
- a plurality of display elements, each display element includinga pixel, anda display circuit electrically connected to the pixel includinga plurality of memory cells, anda selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time;
wherein a first display element has a display circuit of second display element at least partially positioned inside a footprint of the pixel of the first display element.
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Abstract
A display matrix is provided comprising a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel and at least partially positioned outside of a footprint of the pixel, the display circuit including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.
88 Citations
29 Claims
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1. A display matrix comprising:
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a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; wherein a first display element has a display circuit of second display element at least partially positioned inside a footprint of the pixel of the first display element. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A display matrix comprising:
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a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; two or more data lines comprising a first data line which carries a bit signal, and a second data line which carries a bit bar signal, the data lines enabling reading from and writing to the first and second display circuits, each data line electronically connected to both a first display circuit of a first display element and a second display circuit of a second display element.
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9. A display matrix comprising:
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a first display element including a first pixel, and a first display circuit including a plurality of memory cells electrically connected to the first pixel; a second display element including a second pixel, and a second display circuit including a plurality of memory cells electrically connected to the second pixel, the second display circuit being at least partially positioned within a footprint of the second pixel and within a footprint of the first pixel. - View Dependent Claims (10, 11)
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12. A virtual image display system comprising:
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a display matrix including a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel and at least partially positioned outside of a footprint of the pixel, the display circuit including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time, wherein a first display element has a display circuit of second display element at least partially positioned inside a footprint of pixel of the first display element; peripheral control circuits for controlling read and write operations to the memory cells; and one or more magnification optics for magnifying the sub-images formed by the display matrix. - View Dependent Claims (13, 14, 15, 16)
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17. A virtual image display system comprising:
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a display matrix comprising a first display element including a first pixel, and a first display circuit including a plurality of memory cells electrically connected to the first pixel, a second display element including a second pixel, and a second display circuit including a plurality of memory cells electrically connected to the second pixel, the second display circuit being at least partially positioned within a footprint of the second pixel and within a footprint of the first pixel; peripheral control circuits for controlling read and write operations to the memory cells; and one or more magnification optics for magnifying the sub-images formed by the display matrix. - View Dependent Claims (18, 19, 20)
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21. A method for reducing the number of address lines in a pixel-based display system, the method comprisng:
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electrically connecting a plurality of display circuits to a plurality of pixels each having a footprint, each display circuit having an electrical connection to only one pixel, the plurality of display circuits controlling the operation of the plurality of pixels; positioning the plurality of display circuits relative to the plurality of pixels such that at least a portion of the plurality of display circuits is positioned within a footprint of at least two pixels; and connecting data lines to the plurality of data circuits to read and write data to the plurality of data circuits. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method for reducing the number of address lines in a pixel-based display system, the method comprising:
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electrically connecting a plurality of display circuits to a plurality of pixels each having a footprint, each display circuit having an electrical connection to only one pixel, the plurality of display circuits controlling the operation of the plurality of pixels; positioning the plurality of display circuits relative to the plurality of pixels such that a first display element has a display circuit of second display element at least partially positioned inside the footprint of a pixel of a first display element; and connecting data lines to the plurality of data circuits to read and write data to the plurality of data circuits.
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28. A method for reducing the number of address lines in a pixel-based display system, the method comprisng:
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electrically connecting a plurality of display circuits to a plurality of pixels each having a footprint, each display circuit having an electrical connection to only one pixel, the plurality of display circuits controlling the operation of the plurality of pixels; positioning the plurality of display circuits relative to the plurality of pixels such that at least a portion of the plurality of pixels have at least two display circuits positioned within the footprint of a given pixel; and connecting data lines to the plurality of data circuits to read and write data to the plurality of data circuits.
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29. A display matrix comprising:
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a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel including a plurality of memory cells, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time; wherein at least a portion of the display circuit is positioned within a footprint of at least two different pixels and the display circuit is electrically connected to only one pixel.
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Specification