Image generating apparatus with FIFO memory and cache memory

• US 6,141,025 A
• Filed: 02/02/1998
• Issued: 10/31/2000
• Est. Priority Date: 02/06/1996
• Status: Expired due to Term

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Oka, Masaaki, Hiroi, Toshiyuki
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US08/930,588
• Time in Patent Office: 1,002 Days
• Field of Search: 345/418-432, 345/501-509, 345/511, 345/513, 345/515, 345/520, 345/521, 345/197, 345/203, 711/3, 711/117, 711/118
• US Class Current: 345/531
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Data from a main part of a drawing engine 101 is sent to and transiently stored in a first-in-first-out (FIFO) memory 102 for storage transiently therein and is supplied via an operating device 103 to a fast cache memory 104 where data exchange is carried out with a frame buffer 105. A cache controller 106 controls the cache memory 104 for pre-reading the contents of the FIFO memory 102 and collectively reading/writing data of the same page in the frame buffer 105 which is accessible at a high speed. This enables fast accessing using an inexpensive frame buffer to improve the drawing speed.

Claims

1. A picture generating apparatus comprising:

drawing means for generating pixel data items each including an address and pixel data according to picture information sequentially;

a transient memory for storing the pixel data items generated by the drawing means and for generating pixel data items sequentially from the stored pixel data;

a cache memory;

a frame memory for storing pixel data;

first control means for writing pixel data of the output pixel data items into the cache memory according to addresses thereof; and

second control means for reading an address of the pixel data item stored in the transient memory before the pixel data item is output,

wherein the second control means retrieves pixel data in the cache memory to detect pixel data whose address has a given part of the same value as that of the read address and which satisfies a given condition, and accesses the frame memory to cache pixel data located at the read address and pixel data located at the address of the detected pixel data, into the cache memory at one time.

2. A picture generating apparatus according to claim 1, wherein the given condition is satisfied when the detected pixel data is invalid so as to make it unnecessary for the detected pixel data to remain in the cache memory.

3. A picture generating apparatus according to claim 1, wherein each of the pixel data items includes an operation instruction, and

the first control means performs at least one of Z-buffer processing, anti-aliasing processing, filtering processing, α

-blending processing, semi-transparent processing and pixel re-arraying processing to the output pixel data item according to an operation instruction thereof and writes the processed pixel data into the cache memory.

4. A video game machine comprising the picture generating apparatus according to claim 1.

5. A method used in a picture generating apparatus which comprises drawing means for generating pixel data items each including an address and pixel data according to picture information sequentially, a transient memory for storing the pixel data items generated by the drawing means and for outputting the stored pixel data items sequentially, a cache memory and a frame memory for storing pixel data, comprising the steps of:

writing pixel data of the output pixel data items into the cache memory according to the addresses thereof;

reading an address of the pixel data item stored in the transient memory before the pixel data item is output; and

retrieving in the cache memory to detect pixel data whose address has a given part of the same value as that of the read address and which satisfies a given condition, and accessing the frame memory to cache pixel data located at the read address and pixel data located at the address of the detected pixel data, into the cache memory at one time.