Measurement and inspection of leads on integrated circuit packages

• US 6,141,040 A
• Filed: 12/19/1997
• Issued: 10/31/2000
• Est. Priority Date: 01/09/1996
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Toh, Peng Seng
• Primary Examiner(s): Le, Vu
• Application Number:
  US08/995,057
• Time in Patent Office: 1,047 Days
• Field of Search: 348/87, 348/92, 348/94-95, 348/126, 348/133, 348/125, 382/141, 382/145, 382/147, 356/237, 356/237.4, 356/237.5
• US Class Current: 348/126
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A system of optics, cameras and image processor arrangement capable of capturing images of lead tips of object fields resulting in accurate 3 dimensional positions of all the leads on a Integrated Circuit such as a Quad Flat Package (QFP). The system comprises of a telecentric lens attached to a camera working with an arrangement of mirrors and lighting. The telecentric lens and mirror optical layout splits the acquired image into 2 orthogonal viewing fields of the same lead tips of the QFP. The QFP is placed flat on a pedestal, and for any given side of the QFP, the first field views the lead tips from the front. The second field views the lead tips from the bottom of the IC package. Enhanced lead tip images are acquired by a lighting arrangement that casts illumination on the lead tips only. Electronic processing techniques are used to compute the geometry of the laeds such as global coplanarity, lead standoff and inspection of other lead defects.

Claims

1. An apparatus for inspecting leads of an integrated circuit package, comprising:

a pedestal having a top surface plane for receiving an integrated circuit package with leads extending from one side,

an angled reflector positioned on the pedestal adjacent the top surface plane and beneath the leads of the integrated circuit package to reflect a bottom view of the leads, and

an imaging system arranged on said one side of the integrated circuit package to acquire an image, the image comprising a direct side view of the leads, and the bottom view of the leads reflected by the reflector, the side and bottoms views being substantially orthogonal.

2. An apparatus as claimed in claim 1, further comprising a light source arranged on said one side of the integrated circuit for front-illuminating the leads.

3. An apparatus as claimed in claim 1, further comprising a processor for processing the image of the side and bottom views of the leads to determine the relative positions of the leads.

4. An apparatus as claimed in claim 3, wherein the processor includes an edge detection algorithm to detect the edges of the leads from the image of the side and bottom views.

5. An apparatus as claimed in claim 1, wherein the imaging system comprises a telecentric lens and a camera, the lens receiving a direct side view of the leads and the bottom view of the leads reflected by the reflector, and relaying the side and bottom views to the camera.

6. A method of inspecting leads of an integrated circuit package, comprising:

providing a pedestal having a top surface plane,

positioning on the top surface plane of the pedestal an integrated circuit package with leads extending from one side,

providing an angled reflector adjacent the top surface plane of the pedestal and beneath the leads of the integrated circuit package to reflect a bottom view of the leads, and

providing an imaging system on said one side of the integrated circuit package to acquire an image, the image comprising a direct side view of the leads, and the bottom view of the leads reflected by the reflector, the side and bottoms views being substantially orthogonal.