System and method for control of low frequency input levels to an amplifier and compensation of input offsets of the amplifier

• US 6,141,169 A
• Filed: 10/23/1997
• Issued: 10/31/2000
• Est. Priority Date: 10/23/1997
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Pietruszynski, David M., Hein, Jerrell P., Bliss, William G., Feyh, German S.
• Primary Examiner(s): KIM, WON TAE C
• Application Number:
  US08/956,569
• Time in Patent Office: 1,104 Days
• Field of Search: 360/67, 360/46, 360/61, 360/25, 369/48, 369/59, 330/259, 330/260
• US Class Current: 360/67
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 2005/0013 of transducers, e.g. linearisation, equalisation
• CPC Class Codes: G11B 5/09 Digital recording
• CPC Class Codes: G11B 7/0941 Methods and circuits for servo gain or phase compensation during operation for initialising servos G11B7/0945
• CPC Class Codes: G11B 7/0948 specially adapted for detection and avoidance or compensation of imperfections on the carrier, e.g. dust, scratches, dropouts G11B7/095 takes precedence
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45748 by using a feedback circuit
• CPC Class Codes: H03F 3/45973 by using a feedback circuit

Abstract

A system and method for an amplifier control circuit is provided which does not require the use of a large off-chip or on-chip capacitor for achieving a low frequency coupling corner, while still effectively allowing AC coupling the data detection circuit. In addition, the input offset voltage to the amplifier may be compensated and the inherent random low frequency input voltages provided to the amplifier may be controlled or canceled. Further, the amplifier control circuitry includes a freeze capability which allows the control circuitry to halt all updates to the input offset/low frequency control circuit when the voltage input signal is interrupted. In addition low frequency control and offset compensation updates may be performed without causing large output signal glitches so that the integrity of the received signal will not be compromised. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.

Claims

1. A method of controlling the output of an amplifier, comprising:

amplifying a data signal with the amplifier to generate an amplifier output, the data signal including unwanted low frequency variations and the amplifier exhibiting input offsets;

coupling a control loop between an amplifier input node that receives the data signal and the amplifier output node; and

compensating the input offset of the amplifier and controlling the low frequency content of the data signal with the control loop to minimize offset voltages and low frequency signals at the amplifier output node.

2. The method of claim 1, further comprising:

interrupting the compensating and controlling step when a disturbance in the data signal occurs.

3. The method of claim 2, the amplifier being a differential amplifier.

4. The method of claim 3, the control loop being coupled to only one input of the amplifier.

5. A method of operating an electrical circuit, comprising:

providing a single ended input signal to a first input node of a differential amplifier;

providing a control loop from an output of the amplifier to the first input node; and

matching the amplifier input impedance at the second input node to the amplifier input impedance of the first input node.

6. The method of claim 5, further comprising:

compensating the amplifier input offset and controlling the low frequency content of the data signal with the control loop to minimize offset voltages and low frequency signals at the amplifier output node.

7. The method of claim 6, further comprising:

interrupting the compensating and controlling step when a disturbance in the data signal occurs.

8. The method of claim 6, the matching being accomplished at least in part by replicating at least a portion of the control loop at the second input node.

9. A data detection circuit capable of being coupled to a data storage medium to receive a data signal, comprising:

an amplifier within the data detection circuit, the amplifier coupled to the data signal; and

means for simultaneously compensating the input offset voltage of the amplifier and controlling the low frequency content of the data signal, the means also allowing the compensation and control to be halted in a hold state, the means comprising a control loop coupled between an input and an output of the amplifier, the control loop comprising a charge pump and a storage capacitor.

10. The circuit of claim 9, the amplifier being a differential amplifier, the control loop being coupled only to one input of the differential amplifier.

11. A data detection circuit, comprising:

a plurality of differential data inputs, the differential data inputs capable of receiving data from a data storage medium;

at least one differential amplifier;

a first amplifier input node of the differential amplifier coupled to at least one of the plurality of differential data inputs;

a second amplifier input node of the differential amplifier coupled to at least one of the plurality of differential data inputs;

a control loop coupled to the first amplifier input node and to at least one output node of the differential amplifier; and

an impedance matching circuit coupled to the second amplifier input node, the impedance matching circuit creating an input impedance at the second amplifier input node that matches an input impedance at the first amplifier input node.

12. The circuit of claim 11, the control loop generating a control signal, the control signal being provided to the first input to compensate for input offsets and control low frequency content of the data signal.

13. The circuit of claim 11, further comprising:

a data disturbance signal coupled to the control loop, the control loop responsive to the data disturbance to interrupt a control signal of the control loop.

14. The circuit of claim 12, further comprising:

a data disturbance signal coupled to the control loop, the control loop responsive to the data disturbance to interrupt a control signal of the control loop.