DRAM and SRAM memory cells with repressed memory
First Claim
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1. A memory cell comprising:
- at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information.
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Abstract
The transfer device of a typical DRAM cell is replaced with a transistor having an additional gate. The unique cell can be accessed as a typical DRAM cell by reading from or writing to a storage capacitor or as a nonvolatile memory by storing charges on the additional gate. Thus, a DRAM cell having a nonvolatile memory component within its cell is formed in a simple and cost effective manner. Transistors in a typical SRAM cell are also replaced by the transistors with the additional gate to form a SRAM cell having a nonvolatile component built within its cell.
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Citations
83 Claims
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1. A memory cell comprising:
at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory cell comprising:
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a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory cell, comprising:
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first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A memory circuit comprising:
a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. A memory circuit comprising:
a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. A memory circuit comprising:
a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and a control circuit for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes. - View Dependent Claims (45, 46, 47, 48, 49, 50)
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51. A processor-based system, comprising:
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a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; at least one transistor, said transistor being operable in a first volatile memory mode of operation to access first information from a first source of information and providing said first information at an output and a second nonvolatile mode of operation to access second information from a second source of stored information and providing said second information at said output, wherein said first information is accessible without affecting said second information and said second information is accessible without affecting said first information. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59)
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60. A processor-based system, comprising:
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a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; a transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, said first gate being coupled to a word line input, one of said source and drain regions being coupled to a bit line input, said second gate being positioned between said first gate and said channel region; and a data storage capacitor coupled between a first voltage and the other of said source and drain region not connected to said bit line input, wherein said transistor is controllable to access a first charge representing a data value from said capacitor in a first mode of operation and a second charge representing a data value from said second gate in a second mode of operation, wherein said first charge is accessible without affecting said second charge and said second charge is accessible without affecting said first charge. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68)
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69. A processor-based system, comprising:
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a processor; a memory circuit coupled to said processor, said memory circuit comprising a plurality of memory cells organized as an array of rows and columns, at least one memory cell comprising; first and second transistors, each transistor having a source region, drain region, channel region between said source and drain regions, and a first gate and second gate, each second gate being positioned between its respective first gate and channel, said first gate of said first transistor is connected to a first node, said first gate of said second transistor is connected to a second node, said first and second nodes being connected to a first voltage, said source and drain regions of said first transistor being connected between said second node and a second voltage, said source and drain regions of said second transistor being is connected between said first node and the second voltage; and control circuitry for coupling said first and second nodes to bit line inputs, each of said nodes having a respective potential representative of data stored in said cell, wherein data is stored in said cell by activating one of said transistors and deactivating the other transistor in a first mode of operation and by storing a first charge on said first transistor and a second charge on said second transistor in a second mode of operation, and wherein only the bit line inputs and a word line input are used by said control circuit to store data in said cell in both said first and second modes. - View Dependent Claims (70, 71, 72, 73, 74, 75)
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76. A method of reading information from a memory cell comprising at least one transistor, said method comprising the steps of:
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reading first information from a first source of stored information in a first volatile memory mode of operation; and reading second information from a second source of stored information in a second nonvolatile mode of operation, wherein said first information is read without affecting said second information and said second information is read without affecting said first information. - View Dependent Claims (77, 78)
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79. A method of reading information from a memory cell comprising a transistor having a control gate and a floating gate and a storage capacitor connected to said transistor, said method comprising the steps of:
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reading a data value from the capacitor in a first mode of operation of the cell; and reading a data value from the floating gate in a second mode of operation of the cell, wherein the reading of a data value from the capacitor does not affect contents of the data value on the floating gate and the reading of a data value from the floating gate does not affect contents of the data value on the capacitor. - View Dependent Claims (80, 81, 82, 83)
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Specification