DRAM that stores multiple bits per storage cell

• US 6,141,261 A
• Filed: 12/31/1999
• Issued: 10/31/2000
• Est. Priority Date: 12/31/1999
• Status: Expired due to Term

• Current Assignee: Robert Patti
• Original Assignee: Robert Patti
• Inventors: Patti, Robert
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/476,625
• Time in Patent Office: 305 Days
• Field of Search: 365/189.07, 365/45, 365/210
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A memory constructed from a plurality of data storage words. Each data storage word includes a plurality of data storage cells and a plurality of reference storage cells, each data storage cell and each reference storage cell having at least 4 states. The memory has a plurality of reference lines, one such reference line corresponding to each reference storage cell. The corresponding reference storage cell is connected to that reference line by a gate included in that storage cell. Each reference cell assumes one of the states in response to a signal on the corresponding reference line and a write signal, the state being determined by the signal on the corresponding reference line. The memory also includes a plurality of data lines, one such data line corresponding to each data storage cell, the corresponding data storage cell being connected to that data line by a gate in that storage cell. Each data cell assumes one of the states in response to a signal on the corresponding data line and a write signal, the state being determined by the signal on the corresponding data line. A plurality of reference encoding circuits determines the state stored by each reference cell, there being one such reference encoding circuit corresponding to each reference line. The preferred data storage cell includes first, second, and third gates, and a capacitor for storing a charge that determines the current sinked by the third gate. The preferred data encoding circuit utilizes a current-mode digital to analog converter. Data is read from the memory by a plurality of data decoding circuits that generate a digital value representing the current flowing in the corresponding data line by comparing that current to currents flowing in each of the reference lines.

Claims

1. A memory comprising:

a plurality of data storage words, each data storage word comprising a plurality of data storage cells and a plurality of reference storage cells, each data storage cell and each reference storage cell having at least 4 states;

a plurality of reference lines, one such reference line corresponding to each reference storage cell, said corresponding reference storage cell being connected to that reference line, each reference storage cell comprising a gate for connecting that storage cell to said corresponding reference line, each reference cell assuming one of said states in response to a signal on said corresponding reference line and a write signal, said state being determined by said signal on said corresponding reference line;

a plurality of data lines, one such data line corresponding to each data storage cell, said corresponding data storage cell being connected to that data line, each data storage cell comprising a gate for connecting that storage cell to said corresponding data line, each data cell assuming one of said states in response to a signal on said corresponding data line and a write signal, said state being determined by said signal on said corresponding data line;

a plurality of reference encoding circuits, one such reference encoding circuit corresponding to each reference line and being connected to that reference line, each reference encoding circuit generating a reference signal on said corresponding reference line in response to said write signal; and

a plurality of data encoding circuits, one such data encoding circuit corresponding to each data line and being connected to that data line, each data encoding circuit comprising a circuit for receiving a digital value having at least 4 states and for generating a data programming signal on said corresponding data line in response to said write signal.

2. The memory of claim 1 wherein said data storage cells comprise a first gate for connecting said storage cell to one of said data lines, a capacitor, a second gate for connecting said capacitor to that data line, and a third gate having a base connected to said capacitor, said third gate sinking a current determined by said charge on said capacitor when said third gate is connected to said data line.

3. The memory of claim 1 wherein said data encoding circuit comprises a current-mode digital to analog converter.

4. The memory of claim 1 further comprising a plurality of data decoding circuits, one such data decoding circuit corresponding to each data line and being connected to that data line, each data decoding circuit comprising a current mode analog to digital converter for generating a digital value representing the current flowing in said corresponding data line by comparing that current to currents flowing in each of said reference lines.

5. The memory of claim 4 wherein said current mode analog to digital converter utilizes a piecewise linear curve defined by said currents flowing in each of said reference lines.