Single chip communication device that implements multiple simultaneous communication channels

• US 6,141,376 A
• Filed: 04/01/1997
• Issued: 10/31/2000
• Est. Priority Date: 04/01/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Shaw, Carl
• Primary Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/831,405
• Time in Patent Office: 1,309 Days
• Field of Search: 375/222, 375/257, 395/200.8, 709/250, 370/463, 370/319, 370/464
• US Class Current: 375/222
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A single chip communications controller responsive to control program commands, implements at least three major communication function standards simultaneously by using a superscalar processor coupled to a multi-functional communication interface unit, and a supportive memory system via a common communication bus.

Claims

1. A single chip multi-port communication device, comprising:

an integrated circuit substrate;

a multi-channel interface unit formed on said substrate for providing a plurality of simultaneous communication channels to effect bi-directional transmission of data, wherein said multi-channel interface unit includes a pair of simultaneous analog communications channels and a pair of simultaneous digital communication channels, wherein one of a pair of microprocessors controls one of the analog channels and one of the digital channels, and wherein the other one of the pair of microprocessors controls the other one of the analog channels and the other one of the digital channels;

the pair of microprocessors formed on said substrate for processing the bi-directional transmission of data simultaneously via said plurality of communication channels; and

a bus formed on said substrate for coupling together, for signal processing purposes, said multi-channel interface unit and said pair of microprocessors.

2. A single chip multi-port communication device according to claim 1, wherein at least one of said plurality of simultaneous analog channels includes a UART device.

3. A single chip multi-port communication device according to claim 1, wherein said plurality of simultaneous analog channels includes a pair of UART devices.

4. A single chip multi-port communication device according to claim 1, wherein at least one of said plurality of simultaneous digital channels includes a CODEC device.

5. A single chip multi-port communication device according to claim 1, wherein said plurality of simultaneous digital channels includes a pair of CODEC devices.

6. A single chip multi-port communication device according to claim 1, wherein said pair of microprocessors each include a data buffer and an instruction buffer for facilitation and simultaneous bi-directional transmission of data via said plurality of communication channels.

7. A single chip multi-port communication device according to claim 1, wherein said pair of microprocessors operated at one clock rate and wherein said memory controller means operates at another clock rate;

and said one clock rate being substantially faster than said another clock rate.

8. A single chip multi-port communication device according to claim 7, further comprising:

means for coupling said integrated circuit substrate to a fixed clock rate signal; and

clock generator means formed on said substrate and responsive to said fixed clock rate signal for generating said one clock rate and said another clock rate.

9. A single chip multi-port communication device according to claim 1, wherein said pair of microprocessors are each 32-bit RISC central processing units.

10. A single chip multi-port communication device, comprising:

an integrated circuit substrate;

a multi-channel interface unit formed on said substrate for providing a plurality of simultaneous communication channels to effect bi-directional transmission of data;

a pair of microprocessors formed on said substrate for processing the bi-directional transmission of data simultaneously via said plurality of communication channels;

a bus formed on said substrate for coupling together, for signal processing purposes, said multi-channel interface unit and said pair of microprocessors; and

multiply and accumulate core means formed on said substrate and coupled to said pair of microprocessors for optimizing the number of operational steps to effect simultaneous bi-directional data communications via said multi-channel interface unit.

11. An internet provider system, comprising:

a central processing system for processing data received from a plurality of remote locations;

each remote location including at least one communication channel for effecting bi-directional transmission of data between the remote location and said central processing unit;

said central processing system having;

a local communication integrated circuit including a central processor unit;

a random access memory unit; and

a data interface unit for effecting bi-directional transmission of data between a local system user, said central processor unit, and said random access memory unit; and

interface means for coupling said bus to said random access memory unit for storing programmatic instructions to effect simultaneous bi-directional transmission of data from said plurality of remote locations to said central processor unit, wherein said multi-channel interface unit includes a pair of simultaneous analog communications channels and a pair of simultaneous digital communication channels, wherein one of a pair of microprocessors controls one of the analog channels and one of the digital channels, and wherein the other one of the pair of microprocessors controls the other one of the analog channels and the other one of the digital channels.

12. A communication controller for transmitting and receiving data on at least three communication channels simultaneously, comprising:

a multi-channel interface unit for coupling the communication controller to the at least three communication channels;

memory means for storing computer readable codes indicative of control commands for transmitting and receiving data substantially simultaneously over at least three different communication channels;

a pair of processor means responsive to the computer readable codes and coupled individually to at least two of said least three communication channels;

a single bi-directional interface bus for coupling said multi-channel interface unit and said memory means to said pair of processor means for bi-directional data transfers simultaneously over said at least three communications channels; and

multiply and accumulate core means coupled to said pair of processor means for optimizing the number of operational steps to effect simultaneous bi-directional data communications via said interface bus.

13. A communications controller according to claim 12, wherein each of said pair of processor means is a reduced instruction set computer processor.

14. A communications controller according to claim 12, wherein each of said pair of processor means is a superscalar processor.

15. A communications controller according to claim 12, further comprising a peripheral component interconnect bus interface.

16. A multi-channel communication controller according to claim 12, wherein said memory means includes:

a main memory unit; and

a boot memory for storing computer readable boot code.

17. A multi-channel communication controller according to claim 16, wherein said main memory unit is a SDRAM memory unit.

18. A multi-channel communication controller according to claim 16, wherein said boot memory is a read only memory.

19. A multi-channel communication controller according to claim 12, further comprising a single integrated substrate to accommodate the communication controller in a single expansion slot of a personal computer.

20. A single chip multi-port communication device, comprising:

an integrated circuit substrate;

a multi-channel interface unit formed on said substrate for providing a plurality of simultaneous communication channels to effect bi-directional transmission of data, wherein said multi-channel interface unit includes a pair of simultaneous analog communications channels and a pair of simultaneous digital communication channels;

a pair of microprocessors formed on said substrate for processing the bi-directional transmission of data simultaneously via said plurality of communication channels;

wherein one of the pair of microprocessors controls one of the analog channels and one of the digital channels, and wherein the other one of the pair of microprocessors controls the other one of the analog channels and the other one of the digital channels;

a bus formed on said substrate for coupling together, for signal processing purposes, said multi-channel interface unit and said pair of microprocessors;

means for coupling said bus to an external random access memory unit for storing programmatic instructions to effect simultaneous bi-directional transmission of data; and

memory controller means responsive to said pair of microprocessors for retrieving the programmatic instruction from said external random access memory unit to instruct the microprocessor on the procedures for moving data between said external random access memory unit and said multi-channel interface unit.