Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
First Claim
1. An output interface for a sender of data, comprising:
- an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal;
an input for providing a request signal from a receiver and asynchronous with the reference clock signal indicating a request for transfer of data from the sender; and
a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum.
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Accused Products
Abstract
An interface enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls the flow of data between the processing elements. The flow control allows the processing elements to be data independent, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format, or other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats and precisions. Flow of data between processing elements may be controlled by handshake signals indicating whether the data output by the sender is valid and whether the receiver can receive data. The sender transmits data and asserts a valid signal along with the data in response to a request signal from the receiver. The request signal may be asserted by the receiver and responded to asynchronously by the sender with the transmission of the data by the sender. As a result, the sender and receiver are decoupled, thus enabling high speed data transmission and time division multiplexing of data across the interconnect. The sender also may transfer command data. A valid command signal is to indicate the present of command data.
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Citations
48 Claims
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1. An output interface for a sender of data, comprising:
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an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver and asynchronous with the reference clock signal indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An input interface for a receiver of data, comprising:
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an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated and synchronous with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal asynchronous with the reference clock signal and indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted and at a rate defined by the reference clock signal. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An output interface for a sender of data, comprising:
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an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with data and indicating whether the associated data is valid and a valid command signal associated with a command data and indicating whether the associated command data is valid command data; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that transfers data with one of the valid data signal and the valid command signal asserted when a request signal is received.
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28. An input interface for a receiver of data, comprising:
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an input for receiving from a sender data and a boundary signal indicating whether the data defines a boundary of a sample of the data and a valid data signal associated with the data and indicating whether the data is valid and a valid command signal associated with the data and indicating whether the data is valid command data; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when one of the valid data signal and the valid command signal is asserted.
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29. An output interface for a sender of data, comprising:
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an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; and a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum, wherein the output further provides a valid command signal associated with a datum and indicating whether the associated datum is valid command data. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. An output interface for a sender of data, comprising:
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an output for providing a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal and wherein the data is output by the output interface at a rate defined by the reference clock signal; an input for providing a request signal from a receiver indicating a request for transfer of data from the sender; a controller that, after receipt of the request signal, directs data to the output and that asserts the valid data signal in association with the datum; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop. - View Dependent Claims (37, 38)
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39. An input interface for a receiver of data, comprising:
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an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data and a valid data signal associated with a datum and indicating whether the associated datum is valid; an output for providing a request signal indicating a request for transfer of data from the sender; and a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted wherein the input further receives a valid command signal associated with a datum and indicating whether the associated datum is valid command data. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. An input interface for a receiver of data, comprising:
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an input for receiving from a sender a datum and a boundary signal indicating whether the datum defines a boundary of a sample of the data, a valid data signal associated with a datum and indicating whether the associated datum is valid, and a reference clock signal; an output for providing a request signal indicating a request for transfer of data from the sender; a controller that issues the request signal when the input interface is capable of receiving data and that reads the datum from the input when the valid data signal in asserted, wherein the data is read by the controller at a rate defined by the reference clock signal; and a phase-lock loop having an input for receiving the reference clock signal and an output providing a clock signal having a rate higher than a rate of the reference clock signal and wherein the rate defined by the reference clock signal is the rate defined by the output of the phase-lock loop. - View Dependent Claims (47, 48)
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Specification