Method and apparatus to enable insertion/ejection of a device in a computer system while maintaining operation of the computer system and application software

• US 6,141,711 A
• Filed: 12/19/1996
• Issued: 10/31/2000
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kotlowski, Kenneth J., Shah, Pranay D., Ma, Kenneth C., Hawkey, Jeffrey A.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/769,998
• Time in Patent Office: 1,412 Days
• Field of Search: 395/281-283, 395/287-288, 395/306-309, 395/556, 395/560, 395/878, 395/880, 395/881
• US Class Current: 710/302
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

A secondary bus controller allows for hot insertion and ejection of devices from the secondary bus without ceasing operations or halting software in the host computer. When a device is to be inserted a signal is sent to the secondary bus controller. The secondary bus controller suspends operation of the secondary bus, placing devices on the secondary bus in stasis. An interrupt handler reconfigures the system for the newly inserted card once it has been inserted. Attempts to access devices on the secondary bus during the insertion process may be met with a retry signal until insertion is complete. The ejection process follows similar steps, isolating and suspending operations on the secondary bus and triggering an interrupt routine in the host processor to reconfigure the system. The host processor and primary busses, along with the secondary bus controller remain active throughout the insertion or ejection processes. Thus, applications running on the host computer need not be terminated during insertion or ejection. The present invention has particular application to network server computer systems.

Claims

1. A method for allowing insertion and removal of a device into an operational computer system without disrupting processing on the computer system, comprising the steps of:

providing a secondary bus for receiving devices to be inserted and ejected from the computer system;

providing a secondary bus controller coupled to a primary bus in the computer system;

receiving, in the secondary bus controller, a first signal indicating a device is to be inserted or removed;

stopping a bus clock on the secondary bus in response to the first signal so as to halt processing on devices coupled to the secondary bus;

allowing insertion and removal of a device from the secondary bus;

receiving a second signal indicating that a device has been inserted or removed;

restarting the bus clock on the secondary bus in response to the second signal;

reconfiguring the computer system for devices present on the secondary bus;

determining, in the secondary bus controller, whether a device is to be inserted or removed and setting a bit in the secondary bus controller indicating whether a device is to be inserted or removed; and

signalling, in response to the first signal, an interrupt routine in the host processor, said interrupt routine comprising the steps of;

determining, from the first signal and the bit, whether a device is to be removed or inserted;

determining, if a device is to be inserted, whether the device has been inserted into the secondary peripheral bus in response to the second signal;

setting, in the secondary peripheral bus controller, a bit indicating the secondary peripheral bus controller clock is to be started for the newly inserted device; and

setting in the secondary bus controller a bit indicating that the reset signal to the device inserted is to be deasserted.

2. The method of claim 1, wherein said interrupt routine further comprises the step of:

generating a signal to activate a device lock to physically lock the device to the secondary bus.

3. The method of claim 2, wherein the secondary bus controller generates a retry signal to applications attempting access devices on the secondary bus during insertion and removal of a device.

4. The method of claim 1, further comprising the steps of:

stopping bus power on the secondary bus in response to the first signal;

restarting power to the secondary bus in response to the second signal.

5. A method for allowing insertion and removal of a device into an operational computer system without disrupting processing on the computer system, comprising the steps of:

providing a secondary bus for receiving devices to be inserted and ejected from the computer system;

providing a secondary bus controller coupled to a primary bus in the computer system;

receiving, in the secondary bus controller, a first signal indicating a device is to be inserted or removed;

stopping a bus clock on the secondary bus in response to the first signal so as to halt processing on devices coupled to the secondary bus;

allowing insertion and removal of a device from the secondary bus;

receiving a second signal indicating that a device has been inserted or removed;

restarting the bus clock on the secondary bus in response to the second signal;

reconfiguring the computer system for devices present on the secondary bus;

and wherein said step of restarting the bus clock on the secondary bus comprises the steps of;

asserting a reset signal to a newly inserted device on the secondary bus;

restarting the bus clock to the newly inserted device substantially simultaneously with the assertion of the reset signal;

deasserting the reset signal to the newly inserted device on the secondary bus; and

restarting the bus clock to devices other than the newly inserted device on the secondary bus.

6. A method for allowing insertion and removal of a device into an operational computer system without disrupting processing on the computer system, comprising the steps of:

providing a secondary bus for receiving devices to be inserted and ejected from the computer system;

providing a secondary bus controller coupled to a primary bus in the computer system;

receiving, in the secondary bus controller, a first signal indicating a device is to be inserted or removed;

stopping a bus clock on the secondary bus in response to the first signal so as to halt processing on devices coupled to the secondary bus;

allowing insertion and removal of a device from the secondary bus;

receiving a second signal indicating that a device has been inserted or removed;

restarting the bus clock on the secondary bus in response to the second signal;

reconfiguring the computer system for devices present on the secondary bus; and

signalling, in response to the first signal, an interrupt routine in the host processor, said interrupt routine comprising the steps of;

determining, from the first signal, whether a device is to be removed or inserted; and

closing system resources accessing a device to be removed if a device is to be removed.

7. The method of claim 6, further comprising the steps of:

signalling, in response to the second signal, an interrupt routine in the host processor, said interrupt routine comprising the steps of;

determining whether a device has been removed from the secondary bus; and

determining which device on the secondary bus has been removed from the secondary bus,

wherein said step of reconfiguring the computer system for devices on the secondary bus comprises the step of removing configuration information for the device removed from the secondary bus.

8. The method of claim 7, wherein the secondary bus controller generates a retry signal in response to access requests from the computer system during insertion and removal of a device.

9. A computer system comprising:

at least one host processor;

a host bus, coupled to said at least one host processor, for transmitting data and address information to and from said at least one host processor;

a system controller, coupled to said host bus, for interfacing said at least one host processor to at least one device;

a primary bus, coupled to said system controller, for coupling said system controller to at least one device;

a secondary bus controller, coupled to said primary bus and operating as a device on said primary bus, for interfacing at least one removable device to said at least one host processor;

a secondary bus, coupled to said secondary bus controller, for coupling at least a removable device to said secondary bus controller;

a connector, coupled to said secondary bus, for receiving and connecting at least one removable device to said secondary bus;

removable device presence detection means, coupled to said secondary bus controller, for indicating presence of a removable device;

an insertion request means, coupled to said secondary bus controller, for receiving an insertion request signal indicating a request to insert a device into said connector;

an eject request means, coupled to said secondary bus controller, for receiving an removal request signal indicating a request to eject a device from said connector;

an insert start means, coupled to said secondary bus controller, for receiving an insertion start signal indicating a device is being inserted into said connector;

wherein said removable device presence detection means comprises a first and second power control signals coupled to said connector, for receiving a signal indicative of a power requirement of a removable device; and

logic means, coupled to said removable device presence detection means and said insert start means, for combining signals from said removable device presence detection means and said insert start means and outputting a removable device presence signal to said secondary bus controller.

10. A computer system of claim 9, wherein said logic means further comprises:

an AND gate and ANDing the first and second power control signals to produce the removable device presence signal to said secondary bus controller.

11. A computer system of claim 9, wherein said logic means further comprises a connection for connecting the first and second power control signals to produce the removable device presence signal to said secondary bus controller.

12. The computer system of claim 9, further comprising:

a notification interrupt means coupling said secondary bus controller and said system controller, for transmitting a interrupt signal to said at least one host processor,

wherein said secondary bus controller generates an interrupt signal upon insertion and removal of a removable device from said connector.

13. The computer system of claim 12, further comprising:

a secondary bus clock line for transmitting clock signals to said connector,

wherein said secondary bus controller controls clock signals over said secondary bus clock line to said connector to suspend clock signals to said connector upon receipt of a removal request signal on said removal request means and up on receipt of a insert request signal on said insertion request means.

14. The computer system of claim 13, further comprising:

a secondary bus reset means for transmitting reset signals to said connector,

wherein said secondary bus controller de-asserts reset signals over said secondary bus reset means to devices present in said connector prior to insertion and removal, and said secondary bus controller asserts are set signal to a device inserted into said connector after said device has been inserted.

15. A secondary bus controller comprising:

first means for interfacing said bus controller with a primary bus interface so as to configure said secondary bus controller as a device on said primary bus interfaces;

second means for interfacing said secondary bus controller with a secondary bus; and

a secondary bus clock control means for controlling secondary bus clock signals to one or more removable devices on the secondary bus;

a secondary bus reset control means for controlling secondary bus reset signals to one or more removable device on the secondary bus; and

wherein said secondary bus clock signals are stopped during insertion and removal of a device on said secondary bus; and

wherein a reset signal is asserted on said secondary bus reset control means to a newly inserted device when the device is inserted into the secondary bus; and

wherein clock signals to the newly inserted device on the secondary bus are started substantially simultaneously with assertion of the reset signal to the newly inserted device.

16. The secondary bus controller of claim 15, wherein clock signals to other devices on the secondary bus are restarted substantially simultaneously with deassertion of the reset signal to the newly inserted device.

17. A secondary bus controller comprising:

first means for interfacing said bus controller with a primary bus interface so as to configure said secondary bus controller as a device on said primary bus interface;

second means for interfacing said secondary bus controller with a secondary bus;

a secondary bus clock control means for controlling secondary bus clock signals to one or more removable devices on the secondary bus;

a notification interrupt means, for coupling the secondary bus controller with a system controller and for transmitting an interrupt signal to the system controller when a device is inserted or removed from the secondary bus;

an ejection request means for receiving a signal indicating a request to remove a device from the secondary bus; and

an insert request means, for receiving a signal indicating a request to insert a device into the secondary bus.

18. The secondary bus controller of claim 17, wherein said notification interrupt means generates an a first interrupt signal upon insertion of a device into the secondary bus, a second interrupt signal upon indication of a request to remove a device from the secondary bus, and a third interrupt signal upon removal of a device from the secondary bus.