System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word

• US 6,141,747 A
• Filed: 09/22/1998
• Issued: 10/31/2000
• Est. Priority Date: 09/22/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Witt, David B.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/158,465
• Time in Patent Office: 770 Days
• Field of Search: 712/225, 712/218, 712/23, 711/122, 711/138, 711/169, 711/140
• US Class Current: 712/225
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

A load/store unit searches a store queue included therein for each byte accessed by the load independently from the other bytes, and determines the most recent store (in program order) to update that byte. Accordingly, even if one or more bytes accessed by the load are modified by one store while one or more other bytes accessed by the load are modified by another store, the forwarding mechanism may assemble the bytes accessed by the load. More particularly, load data may be forwarded accurately from an arbitrary number of stores. In other words, forwarding may occur up to N stores (where N is the number of bytes accessed by the load). In one particular embodiment, the load/store unit generates a bit vector from a predetermined set of least significant bits of the addresses of loads and stores. The bit vector includes a bit for each byte in a range defined by the number of least significant bits. The bit indicates whether or not the byte is updated (for store bit vectors) or accessed (for load bit vectors). The load/store unit may then examine the bit vectors (and compare the remaining bits of the store and load addresses, exclusive of the least significant bits used to generate the bit vectors) in order to locate the most recent update of each byte.

Claims

1. A method for forwarding store data accessed by a load from a store queue, the method comprising:

selecting a first byte accessed by said load from a first store queue entry within said store queue, wherein a first store corresponding to said first store queue entry is most recent, in program order, to update said first byte; and

selecting a second byte accessed by said load from a second store queue entry within said store queue, wherein said second store queue entry is different than said first store queue entry, and wherein a second store corresponding to said second store queue entry is most recent, in program order, to update said second byte, and wherein said selecting said second byte is independent of said selecting said first byte.

2. The method as recited in claim 1 further comprising:

generating a load bit vector having a bit corresponding to each byte within a predetermined range defined by a predetermined number of least significant bits of a load address corresponding to said load, and wherein said bit is indicative of whether or not a corresponding byte is accessed by said load;

generating a first store bit vector having a bit corresponding to each byte within a predetermined range defined by said predetermined number of least significant bits of a first store address corresponding to said first store, and wherein said bit is indicative of whether or not a corresponding byte is updated by said first store; and

generating a second store bit vector having a bit corresponding to each byte within a predetermined range defined by said predetermined number of least significant bits of a second store address corresponding to said second store, and wherein said bit is indicative of whether or not a corresponding byte is updated by said second store.

3. The method as recited in claim 2 wherein said selecting a first byte comprises:

examining a corresponding bit within said load bit vector to determine that said first byte is accessed by said load; and

examining a corresponding bit within said first store bit vector to determine that said first store updates said first byte.

4. The method as recited in claim 3 further comprising comparing said load address and said first store address exclusive of said predetermined number of least significant bits, wherein said selecting said first byte is performed responsive to said comparing.

5. The method as recited in claim 4 wherein said selecting a second byte comprises:

examining a corresponding bit within said load bit vector to determine that said second byte is accessed by said load; and

examining a corresponding bit within said second store bit vector to determine that said second store updates said second byte.

6. The method as recited in claim 5 further comprising comparing said load address and said second store address exclusive of said predetermined number of least significant bits, wherein said selecting said second byte is performed responsive to said comparing.

7. The method as recited in claim 2 further comprising storing said first store bit vector in said first store queue entry and storing said second store bit vector in said second store queue entry.

8. The method as recited in claim 1 further comprising selecting a third byte accessed by said load from said store queue independent of said selecting a first byte and said selecting a second byte.

9. The method as recited in claim 8 wherein said selecting a third byte comprises selecting said third byte from said first store queue entry responsive to determining that said first store is most recent, in program order, to update said third byte.

10. The method as recited in claim 8 wherein said selecting a third byte comprises selecting said third byte from said second store queue entry responsive to determining that said second store is most recent, in program order, to update said third byte.

11. The method as recited in claim 1 further comprising allocating said first store queue entry upon executing a store address instruction operation.

12. The method as recited in claim 11 further comprising storing data into said first store queue entry upon executing a store data instruction operation.

13. The method as recited in claim 12 further comprising deriving said store address instruction operation and said store data instruction operation from a single instruction.

14. A load/store unit comprising:

a store queue configured to store addresses and data corresponding to stores which are not yet retired to a data cache; and

forwarding logic coupled to said store queue and to receive a load address, wherein said forwarding logic is configured to determine, independently for each one of a plurality of bytes accessed by a load corresponding to said load address, which one of said stores stored in said store queue is a most recent update of said one of said plurality of bytes, and wherein said forwarding logic is configured to select at least one of said plurality of bytes from one store within said store queue and at least another one of said plurality of bytes from another store within said store queue.

15. The load/store unit as recited in claim 14 further comprising a first bit vector generator coupled to said store queue and to receive a plurality of least significant bits of each store address, wherein said first bit vector generator is configured to generate a store bit vector corresponding to said each store address, and wherein each bit of said store bit vector corresponds to a byte and is indicative of whether or not that byte is updated by said store, and wherein said load/store unit is configured to store said store bit vector in said store queue.

16. The load/store unit as recited in claim 15 further comprising a second bit vector generator coupled to said forwarding logic and to receive a plurality of least significant bits of said load address, wherein said first bit vector generator is configured to generate a load bit vector corresponding to said load address, and wherein each bit of said load bit vector corresponds to a byte and is indicative of whether or not that byte is accessed by a load corresponding to said load address.

17. The load/store unit as recited in claim 16 wherein said forwarding logic is configured to examine said load bit vector and said store bit vector and a result of comparing said load address (exclusive of said plurality of least significant bits) and said store address (exclusive of said plurality of least significant bits) to determine a most recent update for each byte accessed by said load.

18. A processor comprising:

at least one execution core including one or more address generation units, wherein said address generation units are configured to generate load addresses corresponding to loads and store addresses corresponding to stores; and

a load/store unit coupled to said execution core, said load/store unit including a store queue configured to store said store addresses and corresponding store data for stores outstanding within said processor, said load/store unit configured to receive said load addresses and to forward store data corresponding to said loads from said store queue if store data corresponding to said loads is stored therein, wherein said load/store unit is configured to select a particular store within said store queue from which to forward data independently, on a byte by byte basis, for each byte accessed by a particular load.

19. The processor as recited in claim 18 wherein said execution core further comprises a store data unit configured to deliver store data to said load/store unit.

20. The processor as recited in claim 19 wherein said store data unit is configured to deliver store data in response to executing a store data instruction operation.

21. The processor as recited in claim 20 wherein said one or more address generation units comprises a store address generation unit configured to generated said store address in response to a store address instruction operation.

22. The processor as recited in claim 20 wherein said processor is configured to derive said store address instruction operation and said store data instruction operation from a same instruction.

23. The processor as recited in claim 18 further comprising a second execution core coupled to said load/store unit, wherein said second execution core includes one or more address generation units, wherein said address generation units are configured to generate load addresses corresponding to loads and store addresses corresponding to stores.

24. The processor as recited in claim 18 further comprising a data cache coupled to said execution core and said load/store unit, wherein said data cache is configured to provide data accessed by said particular load responsive to a lack of said data in said store queue.

25. The processor as recited in claim 18 wherein said load/store unit is configured to generate a store bit vector corresponding to said particular store, and wherein each bit of said store bit vector corresponds to a byte and is indicative of whether or not that byte is updated by said particular store, and wherein said load/store unit is configured to store said store bit vector in said store queue.

26. The processor as recited in claim 25 wherein said load/store unit is configured to generate a load bit vector corresponding to said particular load, and wherein each bit of said load bit vector corresponds to a byte and is indicative of whether or not that byte is accessed by said particular load.