Error propagation limiting encoder/decoder for multilevel decision feedback equalization

• US 6,141,783 A
• Filed: 04/10/1998
• Issued: 10/31/2000
• Est. Priority Date: 04/10/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ashley, Jonathan James, Blaum, Mario, Melas, Constantin Michael, Marcus, Brian Harry
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/058,509
• Time in Patent Office: 935 Days
• Field of Search: 714/746, 714/758, 714/759, 341/59, 341/68, 341/69, 375/233, 375/341, 375/348, 375/350, 375/296, 375/285, 375/260, 375/261, 375/265, 375/316, 375/346, 375/349, 708/323, 370/206, 370/506
• US Class Current: 714/746
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

Claims

1. An encoder for generating encoded data signals, comprising:

an input circuit operable to receive an unencoded data signal; and

an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

2. The encoder of claim 1, wherein the code further has a lower run length limit of one and eliminates infinitely propagating error sequences when the encoded data is recovered by a multi-level decision feedback equalizer data recovery channel.

3. The encoder of claim 2, wherein the code has no terminating run length sequences of the form r_i r_i+1 r_i+2 r_i+3 r_i+4 r_i+5 r_i+6 . . . , wherein each r_k is less than a predefined integer.

4. The encoder of claim 3, wherein the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r₁₊₆ . . . , wherein each r_k ≦

4.

5. The encoder of claim 4, wherein

the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k is selected from a set consisting of 3 and 4;

and

the code has no terminating run length sequences of the form 2 2 2 2 2 2 . . .

6. The encoder of claim 1, wherein the encoding circuit comprises:

a state storage device, operable to store and output a signal representing a current state of the encoder, the current state signal having four bits, and having an input operable to accept a four bit next state signal; and

an encoding table having a first input, a second input, a first output, and a second output, wherein the first input is operable to accept a current four bit group of the unencoded data signal, the second input is operable to accept the current state signal, the first output is operable to output a six bit string of the encoded data signal, and the second output is operable to output the next state signal, wherein column values are input on the first input and row values are input on the second input.

7. A circuit for generating decoded data signals, comprising:

an analog to digital converter, coupled to an analog signal representing encoded data, operable to generate a digital signal representing the analog signal;

a decision feedback equalizer, comprising a forward equalizer, coupled to the digital signal, operable to generate an equalized digital signal, a threshold detector, coupled to the equalized digital signal and a feedback signal, operable to generate a data signal, and a feedback equalizer, coupled to the data signal, operable to generate the feedback signal; and

a decoder, coupled to the data signal, operable to generate a decoded data signal;

wherein the encoded data is encoded using a code that eliminates infinitely propagating error sequences.

8. The circuit of claim 7, wherein the decision feedback equalizer is a multi-level decision feedback equalizer and the code has a lower run length limit of one.

9. The circuit of claim 8, wherein the code has no terminating run length sequences of the form r_i r_i+1 r_i+2 r_i+3 r_i+4 r_i+5 r_i+6 . . . , wherein each r_k is less than a predefined integer.

10. The circuit of claim 9, wherein the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . . , wherein each r_k ≦

4.

11. The circuit of claim 10, wherein:

the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k is selected from a set consisting of 3 and 4; and

the code has no terminating run length sequences of the form 2 2 2 2 2 2 . . .

12. The circuit of claim 8, wherein the decoder comprises:

a decoding table having a first input, a second input, and an output, wherein the first input is operable to accept a current six bit string of the data signal, the second input is operable to accept a next six bit string of the data signal, and the output is operable to output a four bit group of the decoded data signal, wherein row values are input on the first input and column values are input on the second input.

13. A decoder for decoding encoded data signals, comprising:

an input circuit operable to receive an encoded data signal; and

a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

14. The decoder of claim 13, wherein the code further has a lower run length limit of one and eliminates infinitely propagating error sequences when the encoded data is recovered by a multi-level decision feedback equalizer data recovery channel.

15. The decoder of claim 14, wherein the code has no terminating run length sequences of the form r_i r_i+1 r_i+2 r_i+3 r_i+4 r_i+5 r_i+6 . . . , wherein each r_k is less than a predefined integer.

16. The decoder of claim 15, wherein the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k ≦

4.

17. The decoder of claim 16, wherein:

the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k is selected from a set consisting of 3 and 4; and

the code has no terminating run length sequences of the form 2 2 2 2 2 2 . . .

18. The decoder of claim 14, wherein the decoding table comprises:

a first input operable to accept a current six bit string of the encoded data signal;

a second input operable to accept a next six bit string of the encoded data signal; and

an output operable to output a four bit group of the decoded data signal, wherein row values are input on the first input and column values are input on the second input.

19. A data storage or transmission system comprising:

an input circuit operable to receive an unencoded data signal;

an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code;

a data transmission or storage media operable to receive the encoded data signal, store or transmit the encoded data signal and output a received encoded data signal;

a decision feedback equalizer data recovery channel operable to receive the received encoded data signal and output a recovered encoded data signal; and

a decoding circuit, operable to receive the recovered encoded data signal and generate a decoded data signal using the code;

wherein the code eliminates infinitely propagating error sequences.

20. The system of claim 19, wherein the decision feedback equalizer data recovery channel is a multi-level decision feedback equalizer data recovery channel and the code further has a lower run length limit of one.

21. The system of claim 20, wherein the code has no terminating run length sequences of the form r_i r_i+1 r_i+2 r_i+3 r_i+4 r_i+5 r_i+6 . . . , wherein each r_k is less than a predefined integer.

22. The system of claim 21, wherein the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k ≦

4.

23. The system of claim 22, wherein

the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k is selected from a set consisting of 3 and 4;

and

the code has no terminating run length sequences of the form 2 2 2 2 2 2 . . .

24. The system of claim 19, wherein the encoding circuit comprises:

a state storage device, operable to store and output a signal representing a current state of the encoder, the current state signal having four bits, and having an input operable to accept a four bit next state signal; and

an encoding table having a first input, a second input, a first output, and a second output, wherein the first input is operable to accept a current four bit group of the unencoded data signal, the second input is operable to accept the current state signal, the first output is operable to output a six bit string of the encoded data signal, and the second output is operable to output the next state signal, wherein column values are input on the first input and row values are input on the second input.

25. The system of claim 24, wherein the decoding circuit comprise:

a first input operable to accept a current six bit string of the encoded data signal;

a second input operable to accept a next six bit string of the encoded data signal; and

an output operable to output a four bit group of the decoded data signal, wherein row values are input on the first input and the column values are input on the second input.

26. A method of storing or transmitting data comprising the steps of:

receiving an unencoded data signal;

encoding the unencoded data signal to form an encoded data signal using a code;

storing the encoded data signal in a data storage media or transmitting the encoded data signal into a data transmission media;

receiving a stored or transmitted encoded data signal from the data storage or transmission media;

recovering a recovered encoded data signal from the stored or transmitted encoded data signal using a decision feedback equalizer data recovery channel; and

decoding the recovered encoded data signal to generate a decoded data signal using the code;

wherein the code eliminates infinitely propagating error sequences.

27. The method of claim 26, wherein the decision feedback equalizer data recovery channel is a multi-level decision feedback equalizer data recovery channel and the code further has a lower run length limit of one.

28. The method of claim 27, wherein the code has no terminating run length sequences of the form r_i r_i+1 r_i+2 r_i+3 r_i+4 r_i+5 r_i+6 . . . , wherein each r_k is less than a predefined integer.

29. The method of claim 28, wherein the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k ≦

4.

30. The method of claim 29, wherein

the code has no terminating run length sequences of the form r_i 2 r_i+2 2 r_i+4 2 r_i+6 . . . , wherein each r_k is selected from a set consisting of 3 and 4;

and

the code has no terminating run length sequences of the form 2 2 2 2 2 2 . . .

31. The method of claim 26, wherein the encoding step comprises the steps of:

storing a four bit signal representing a current state of the encoder, the current state signal having four bits;

outputting a six bit string of the encoded data signal based on the current state signal and on a four bit group of the unencoded data signal, wherein column values correspond to the group of the unencoded data signal and row values correspond to the current state signal;

outputting a four bit next state signal based on the current state signal and on a four bit group of the unencoded data signal, wherein the column values correspond to the group of the unencoded data signal and the row values correspond to the current state signal; and

storing the next state signal to form a new current state signal.

32. The method of claim 31, wherein the decoding step comprises the step of:

outputting a four bit group of the decoded data signal based on a current six bit string of the encoded data signal and on a next six bit string of the encoded data signal, wherein the row values correspond to the current string of the encoded data signal and the column values correspond to the next string of the encoded data signal.