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Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation

  • US 6,143,646 A
  • Filed: 06/03/1997
  • Issued: 11/07/2000
  • Est. Priority Date: 06/03/1997
  • Status: Expired due to Fees
First Claim
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1. A method for forming an integrated circuit structure, the method comprising the steps of:

  • forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall, the first dielectric region comprising a first dielectric material having a first dielectric constant;

    etching a portion of the first dielectric material laterally adjacent the second sidewall of the opening to form a void region;

    filling the void region with a second dielectric region which has a second dielectric constant that is less than the first dielectric constant; and

    filling the opening with a conductive material to form a conductive interconnection, the conductive interconnection having a first sidewall in contact with the first sidewall of the opening and a second sidewall in contact with the second sidewall of the opening.

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