Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation

• US 6,143,646 A
• Filed: 06/03/1997
• Issued: 11/07/2000
• Est. Priority Date: 06/03/1997
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wetzel, Jeffrey Thomas
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LUU, PHO M
• Application Number:
  US08/868,332
• Time in Patent Office: 1,253 Days
• Field of Search: 438/637, 438/622, 438/228, 438/175, 437/228
• US Class Current: 438/637
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02137 the material comprising alkyl silsesquioxane, e.g. MSQ
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.

Claims

1. A method for forming an integrated circuit structure, the method comprising the steps of:

forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall, the first dielectric region comprising a first dielectric material having a first dielectric constant;

etching a portion of the first dielectric material laterally adjacent the second sidewall of the opening to form a void region;

filling the void region with a second dielectric region which has a second dielectric constant that is less than the first dielectric constant; and

filling the opening with a conductive material to form a conductive interconnection, the conductive interconnection having a first sidewall in contact with the first sidewall of the opening and a second sidewall in contact with the second sidewall of the opening.

2. The method of claim 1 wherein the step of filling the void region comprises:

depositing the second dielectric region at a temperature less than room temperature, wherein the second dielectric is a low-K dielectric material.

3. The method of claim 1 wherein the step of filling the void region comprises:

depositing the second dielectric region as a low-K dielectric material having a dielectric constant less than or equal to approximately 3.0 by using a chemical vapor phase deposition process.

4. The method of claim 1 wherein the step of etching comprises:

using both plasma etch processing and wet etch processing.

5. The method of claim 1, wherein the step of forming the first dielectric region includes:

forming a first dielectric region having a first dielectric portion and a second dielectric portion overlying each other and separated from each other by an etch stop region, wherein the opening is a dual in-laid structure through the first dielectric portion and the second dielectric portion;

the step of etching the void region includes

etching the void region through both the first and second dielectric portions; and

the step of filling the void includes

filling the void with a second dielectric region, wherein the second dielectric region forms a low-K dielectric plug adjacent the dual inlaid structure.

6. A method for forming a contact structure, the method comprising the steps of:

forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall;

filling a middle portion of the opening with a low-K dielectric;

filling a portion of the opening on a first side of the middle portion with a first conductive interconnection; and

filling a portion of the opening on a second side of the middle portion with a second conductive interconnection.

7. The method of claim 6 wherein the step of filling the middle portion comprises:

depositing a layer of low-K dielectric material in all of the opening;

masking the low-K dielectric material only over the middle portion; and

exposing the low-K dielectric material to an etchant to removed portions of the low-K dielectric material to form the low-K dielectric within the middle portion of the opening.

8. The method of claim 6 wherein the steps of filling a portion of the opening on a first and second side of the middle portion comprises:

depositing a contiguous layer of metal; and

polishing the metal to form both the first and second conductive interconnections.

9. The method of claim 6 wherein the step of forming a first dielectric region comprises:

forming the first dielectric region having a first dielectric portion and a second dielectric portion overlying the first dielectric portion, the second dielectric portion being separated from the first dielectric portion by an etch stop layer; and

etching through the first dielectric region and the second dielectric region to form a dual in-laid contact structure as the opening.

10. A method for forming a contact structure, the method comprising the steps of:

forming a first dielectric layer;

forming an etch stop layer overlying the first dielectric layer;

forming a second dielectric layer overlying the first dielectric layer;

etching openings into the second dielectric layer;

etching the openings to deepen the openings through the first dielectric layer while also forming interconnect openings in the second dielectric layer resulting in a dual-in-laid structure;

depositing a low-K dielectric material within the interconnect openings;

processing the low-K dielectric material to remove portions of the low-K dielectric material in the interconnect openings to form a low-K dielectric middle portion;

depositing a conductive material; and

processing the conductive material to form a first conductive interconnect within the interconnect opening and adjacent a first sidewall of the low-K dielectric middle portion and a second conductive interconnect within the interconnect opening and adjacent a second sidewall of the low-K dielectric middle portion, whereby the low-K dielectric middle portion separates the first and second conductive interconnects.

11. The method of claim 10 wherein the step of processing the low-K dielectric material comprises:

using chemical mechanical polishing (CMP) to form the low-K dielectric middle portion.

12. The method of claim 10 wherein the step of depositing the low-K dielectric material comprises:

deposing the low-K dielectric material to form a low-K dielectric plug through both the first and second dielectric layers.

13. A method for forming a contact structure, the method comprising the steps of:

forming a first dielectric layer;

forming an etch stop layer overlying the first dielectric layer;

forming a second dielectric layer overlying the first dielectric layer;

etching interconnect openings into the second dielectric layer;

etching contact openings into the first dielectric layer wherein the contact openings lie within the interconnect openings thereby resulting in a dual-in-laid structure;

depositing a low-K dielectric material within the interconnect openings;

processing the low-K dielectric material to remove portions of the low-K dielectric material in the interconnect openings to form a low-K dielectric middle portion;

depositing a conductive material; and

processing the conductive material to form a first conductive interconnect within the interconnect opening and adjacent a first sidewall of the low-K dielectric middle portion and a second conductive interconnect within the interconnect opening and adjacent a second sidewall of the low-K dielectric middle portion whereby the low-K dielectric middle portion separates the first and second conductive interconnects.

14. The method of claim 13 wherein the step of processing the low-K dielectric material comprises:

using chemical mechanical polishing (CMP) to form the low-K dielectric middle portion within the interconnect opening.

15. The method of claim 13 wherein the step of depositing the low-K dielectric material comprises:

deposing the low-K dielectric material with the interconnect opening through the second dielectric layer and at least one contact opening through the first dielectric layer to form a low-K dielectric plug through both the first and second dielectric layers.

16. A method for forming a contact structure, the method comprising the steps of:

forming a first dielectric layer;

forming an etch stop layer overlying the first dielectric layer;

forming a second dielectric layer overlying the etch stop layer;

etching contact openings through the first dielectric layer, and interconnect openings through the second dielectric layer to form a first dual in-laid interconnect structure and a second dual in-laid interconnect structure laterally adjacent one another, the contact openings being surrounded by the first dielectric layer and the interconnect openings being separated by a second dielectric layer middle portion;

forming a masking layer within the first and second dual in-laid interconnect structures;

forming an opening through the masking layer which exposes a portion of the second dielectric layer middle portion;

etching a portion of the second dielectric layer middle portion between the first and second dual in-laid interconnect structure to form a void region; and

forming a low-K dielectric within the void region whereby a low-K dielectric plug is positioned between the first and second dual in-laid interconnect structure.

17. The method of claim 16 further comprising the steps of:

polishing portions of both of the low-K dielectric and the masking layer to form the low-K dielectric plug.

18. The method of claim 16 wherein the step of forming the masking layer comprises:

forming the masking layer as a layer of photoresist.

19. A method for forming a semiconductor structure, the method comprising the steps of:

forming a photoresist layer;

forming a low-K dielectric material over the photoresist layer; and

chemical mechanically polishing top portions of both the low-K dielectric material and the photoresist layer to form a planar top surface.

20. The method of claim 19 wherein the step of chemical mechanically polishing comprises:

polishing to selectively form a low-K dielectric plug between two dual in-laid contact structures.