Semiconductor interconnect interface processing by pulse laser anneal

• US 6,143,650 A
• Filed: 01/13/1999
• Issued: 11/07/2000
• Est. Priority Date: 01/13/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Nogami, Takeshi, Brown, Dirk, Pramanick, Shekhar
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Dung A
• Application Number:
  US09/229,590
• Time in Patent Office: 664 Days
• Field of Search: 483/643, 483/637, 483/638, 483/640, 483/672, 483/308, 483/378
• US Class Current: 438/643
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD

Abstract

A method is provided for forming tantalum/copper barrier/seed layers in semiconductor channels or vias by using a pulsed laser annealing step. The pulsed laser can be controlled to heat the copper seed material for such short periods of time that the copper seed material does not agglomerate but the temperature is high enough to form an intermixed layer with the tantalum.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor with a dielectric layer formed thereon;

forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer;

forming an adhesion/barrier layer to line said dielectric layer in said opening;

forming a seed layer to line said adhesion/barrier layer; and

laser annealing said seed layer whereby said seed layer and adhesion/barrier layer intermix.

2. The method as claimed in claim 1 wherein the step of laser annealing raises the temperature of said seed layer sufficiently to cause intermixing and insufficiently to cause agglomeration.

3. The method as claimed in claim 1 wherein the step of laser annealing raises the temperature of said seed layer to 400°

C. and above for between 10 to 1,000 nanoseconds.

4. The method as claimed in claim 1 wherein the step of laser annealing uses a pulse laser with pulse durations of from 1 to 100 nanoseconds.

5. The method as claimed in claim 1 wherein the step forming said adhesion/barrier layer uses a material selected from a group consisting of tantalum, titanium, tungsten, alloys thereof, compounds thereof, and combinations thereof.

6. The method as claimed in claim 1 wherein the step of forming said seed layer uses a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.

7. The method as claimed in claim 1 including the step of forming a conductive layer over said seed layer;

and said step of forming a conductive layer uses a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.

8. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor with a dielectric layer formed thereon;

forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer;

depositing a tantalum layer to line said dielectric layer in said opening;

depositing a copper layer to line said tantalum layer; and

laser annealing said copper layer whereby said copper layer and tantalum layer intermix.

9. The method as claimed in claim 8 wherein the step of laser annealing raises the temperature of said copper layer sufficiently to cause intermixing and insufficiently to cause agglomeration.

10. The method as claimed in claim 8 wherein the step of laser annealing raises the temperature of said copper layer to about 400°

C. and above for between 10 to 1,000 nanoseconds.

11. The method as claimed in claim 8 wherein the step of laser annealing uses a pulse laser with pulse durations of from 1 to 100 nanoseconds.

12. The method as claimed in claim 8 including the step of forming a conductive layer over said copper layer;

and said step of forming a conductive layer uses a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, compounds thereof, and combinations thereof.