Multilevel wiring structure and method of fabricating a multilevel wiring structure

• US 6,143,658 A
• Filed: 09/17/1999
• Issued: 11/07/2000
• Est. Priority Date: 12/12/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Donnelly, Vincent Michael Jr., Ueno, Kazuyoshi
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/398,977
• Time in Patent Office: 417 Days
• Field of Search: 438/652, 438/653, 438/656, 438/666, 438/667, 438/668, 438/672, 438/675, 438/687
• US Class Current: 438/687
• CPC Class Codes: H01L 21/02065 the processing being a planarization of insulating layers
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners

Abstract

The present invention is directed to a device that has wires on at least two levels. The wires are either copper or a metal containing copper. At lease one via plug formed of copper or a metal containing copper is formed which electrically connects at least one wire on the first level with at least one wire on the second level. The device is fabricated under conditions that remove oxides and other metal that form on the exposed surface of the first level of metal during processing prior to the via plug being formed. The resulting interconnect between the first level of metal and the via plus is substantially non-oxidized copper or copper-containing metal.

Claims

1. A method of fabricating a device with wires on at least two levels thereof comprising:

forming a wire first level of wire in a substrate, wherein the wire is copper or a copper-containing metal;

forming an insulating film over the first level of wire;

forming at least one via in the insulating film, wherein the via communicates with at least one wire in the first level;

forming a barrier metal layer over the surface of the substrate with the via formed therein;

etching the substrate using an anisotropic reactive ion etch so that the barrier metal is selectively removed from at least the bottom of the via;

subjecting the substrate to an oxygen or hydrogen plasma;

immersing the substrate in an aqueous solution of hydrofluoric acid; and

exposing the substrate to a reactant gas for a time sufficient to remove essentially all of the oxide on the exposed surface of the first level metal; and

forming via plugs by depositing copper or a copper containing metal in the via.

2. The method of claim 1 wherein the reactant gas is hexafluoro-acetyl-acetone gas.

3. The method of claim 2 wherein the substrate is maintained under vacuum conditions until after the metal is formed in the via.

4. The method of claim 3 wherein the substrate is exposed to the hexafluoro-acetyl-acetone gas under vacuum.

5. The process of claim 4 wherein the resistivity of a copper or copper-containing connecting portion between the first level of copper or copper-containing metal and the copper or copper-containing via plug is about 1.5×

10^-9 Ω

-cm or less.

6. The method of claim 5 wherein the resistance of the copper-containing metal connecting portion between the first level of copper or copper-containing metal and the copper or copper-containing metal via plug is about 2 Ω

or less.