Method of reducing metal voidings in 0.25 .mu.m AL interconnect

• US 6,143,672 A
• Filed: 05/22/1998
• Issued: 11/07/2000
• Est. Priority Date: 05/22/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Chan, Simon S., Pangrle, Suzette K., Huertas, Robert A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): NGUYEN, HA T
• Application Number:
  US09/084,442
• Time in Patent Office: 900 Days
• Field of Search: 438/778, 438/787, 438/763, 438/788, 438/791, 438/792, 438/958, 438/404, 438/424, 438/435, 438/437
• US Class Current: 438/787
• CPC Class Codes: C23C 16/402 Silicon dioxide
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structure

under a pressure from about 1 mTorr to about 6 mTorr, an O₂ flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W,

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300° C. to about 350° C., or

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390° C. to about 410° C.

Claims

1. A method of depositing a dielectric layer over a stacked interconnect structure, comprising:

providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer;

depositing the dielectric layer over the stacked interconnect structure under a condition selected from the following conditions

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300°

C. to about 350°

C., and

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390°

C. to about 410°

C.

2. The method according to claim 1, wherein the stacked interconnect structure comprises a titanium layer over the substrate, an aluminum layer over the titanium layer, and a titanium nitride layer over the aluminum layer.

3. The method according to claim 1, wherein the stacked interconnect structure comprises a titanium layer over the substrate, an aluminum alloy layer over the titanium layer, and a titanium nitride layer over the aluminum alloy layer.

4. The method according to claim 3, wherein the aluminum alloy layer comprises aluminum and copper.

5. The method according to claim 1, wherein the dielectric layer is a silicon dioxide interlayer dielectric layer.

6. The method according to claim 1, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power form about 900 W to about 1300 W at a temperature from about 300°

C. to about 350°

C.

7. The method according to claim 1, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390°

C. to about 410°

C.

8. The method according to claim 1, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr , an N₂ flow rate from about 8 l to about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 260 sccm to about 290 sccm at a power from about 1000 W to about 1200 W at a temperature from about 310°

C. to about 340°

C.

9. The method according to claim 1, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr , an N₂ flow rate from about 8 l to about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 90 sccm to about 110 sccm at a power from about 1000 W to about 1200 W at a temperature from about 390°

C. to about 410°

C.

10. A method of reducing formation of voidings in a stacked interconnect structure comprising a titanium layer adjacent a layer comprising aluminum, comprising:

providing a substrate having the stacked interconnect structure;

depositing the dielectric layer over the stacked interconnect structure and at least a part of the substrate under a condition selected from the following conditions

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300°

C. to about 350°

C., and

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 7 l to about 11.5 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390°

C. to about 410°

C.

11. The method according to claim 10, wherein the stacked interconnect structure comprises a titanium layer over the substrate, an aluminum layer over the titanium layer, and a titanium nitride layer over the aluminum layer.

12. The method according to claim 10, wherein the stacked interconnect structure comprises a titanium layer over the substrate, an aluminum alloy layer over the titanium layer, and a titanium nitride layer over the aluminum alloy layer.

13. The method according to claim 12, wherein the aluminum alloy layer comprises aluminum and copper.

14. The method according to claim 10, wherein the dielectric layer is a silicon dioxide interlayer dielectric layer.

15. The method according to claim 10, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 8 l about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 260 sccm to about 290 sccm at a power from about 1000 W to about 1200 W at a temperature from about 310°

C. to about 340°

C.

16. The method according to claim 10, wherein the dielectric layer is deposited under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 8 l to about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 90 sccm to about 110 sccm at a power from about 1000 W to about 1200 W at a temperature from about 390°

C. to about 410°

C.

17. A method of depositing a silicon dioxide interlayer dielectric layer over a stacked interconnect structure, comprising:

providing a substrate having at least one stacked interconnect structure comprising a titanium layer adjacent at least one of an aluminum layer and an aluminum alloy layer;

depositing the silicon dioxide interlayer dielectric layer over the stacked interconnect structure under a condition selected from the following conditions

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 8 l to about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 260 sccm to about 290 sccm at a power from about 1000 W to about 1200 W at a temperature from about 310°

C. to about 340°

C., and

under a pressure from about 2 Torr to about 2.8 Torr, an N₂ flow rate from about 8 l to about 11 l, an N₂ O flow rate from about 1 l to about 2 l and a silane flow rate from about 90 sccm to about 110 sccm at a power from about 1000 W to about 1200 W at a temperature from about 390°

C. to about 410°

C.