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DRAM cell having an annular signal transfer region

  • US 6,144,054 A
  • Filed: 12/04/1998
  • Issued: 11/07/2000
  • Est. Priority Date: 12/04/1998
  • Status: Expired due to Term
First Claim
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1. A memory device comprising:

  • a bit line conductor;

    a word line conductor;

    a substrate having a trench with side walls formed in the substrate;

    a signal storage node having a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes; and

    a signal transfer device comprising;

    (i) an annular signal transfer region having an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end,(ii) a first diffusion region coupling the first end of the signal transfer region to the second electrode of the signal storage node,(iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor,(iv) a gate insulator coating the inner surface of the signal transfer region, and(v) a gate conductor coating the gate insulator and coupled to the word line conductor; and

    a conductive coupling member coupling a portion of the outer surface of the signal transfer region to a reference potential.

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