DRAM cell having an annular signal transfer region

• US 6,144,054 A
• Filed: 12/04/1998
• Issued: 11/07/2000
• Est. Priority Date: 12/04/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Mandelman, Jack A., Agahi, Farid
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US09/205,934
• Time in Patent Office: 704 Days
• Field of Search: 257/295, 257/296-310, 438/243-253, 361/302-305
• US Class Current: 257/296
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

Claims

1. A memory device comprising:

a bit line conductor;

a word line conductor;

a substrate having a trench with side walls formed in the substrate;

a signal storage node having a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes; and

a signal transfer device comprising;

(i) an annular signal transfer region having an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end,

(ii) a first diffusion region coupling the first end of the signal transfer region to the second electrode of the signal storage node,

(iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor,

(iv) a gate insulator coating the inner surface of the signal transfer region, and

(v) a gate conductor coating the gate insulator and coupled to the word line conductor; and

a conductive coupling member coupling a portion of the outer surface of the signal transfer region to a reference potential.

2. The memory device according to claim 1 wherein the first electrode of the signal storage node is formed in the substrate adjacent the trench.

3. The memory device according to claim 1 wherein the first electrode and the second electrode are both comprised of the same one of p-type silicon and n-type silicon.

4. The memory device according to claim 1 wherein the signal transfer region of the signal transfer device is doped to an impurity concentration to operate in a fully depleted mode.

5. The memory device according to claim 1 wherein the first diffusion region of the signal transfer device is interior of the side walls of the trench.

6. The memory device according to claim 1 further comprising an annular collar oxide having an outer surface adjacent the side walls of the trench, an inner surface adjacent an upper portion of the second electrode, a first end adjacent an end of the node dielectric, and a second end adjacent the first end of the signal transfer region,

wherein the second electrode comprises polycrystalline silicon, the signal transfer region comprises epitaxial silicon, the second electrode and the signal transfer region merge in a merged region, and the first diffusion region is formed interior of the side walls of the trench in the merged region.

7. The memory device according to claim 1 wherein the signal transfer device has a width defined as a distance around a circumference of the side walls of the trench and a length defined as a distance from the first diffusion region to the second diffusion region and a ratio of width to length greater than 2:

1.

8. The memory device according to claim 1 further comprising an oxide isolation region adjacent the outer surface of the signal transfer region.

9. A memory device comprising:

a bit line conductor;

a word line conductor;

a substrate having a trench with side walls formed in the trench;

a signal storage node having a first electrode, a second electrode comprising polycrystalline silicon formed within the trench, and a node dielectric formed between the first and second electrodes;

a signal transfer device comprising;

(i) an annular signal transfer region, comprising epitaxial silicon, having an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end,

(ii) a first diffusion region, interior of the side walls of the trench, coupling the first end of the signal transfer region to the second electrode of the signal storage node,

(iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor,

(iv) a gate insulator coating the inner surface of the signal transfer region, and

(v) a gate conductor coating the gate insulator and coupled to the word line conductor;

a conductive coupling member coupling a portion of the outer surface of the signal transfer region to a reference potential; and

an annular collar oxide having an outer surface adjacent the side walls of the trench, an inner surface adjacent an upper portion of the second electrode, a first end adjacent an end of the node dielectric, and a second end adjacent the first end of the signal transfer region,

wherein the second electrode and the signal transfer region merge in a merged region, and the first diffusion region is formed in the merged region.

10. The memory device according to claim 9 wherein the signal transfer region of the signal transfer device is doped to an impurity concentration to operate in a fully depleted mode.

11. The memory device according to claim 9 further comprising an oxide isolation region adjacent the outer surface of the signal transfer region exclusive of the portion coupled to the conductive coupling member.

12. An array of memory devices, each memory device comprising:

a bit line conductor;

a word line conductor;

a substrate having a trench with an edgeless side wall formed in the substrate;

a signal storage node having a first electrode formed in the substrate adjacent the trench, a second electrode comprising polycrystalline silicon formed within the trench, and a node dielectric formed between the first and second electrodes, wherein the first and second electrodes are both comprised of the same one of p-type silicon and n-type silicon;

a signal transfer device comprising;

(i) an annular signal transfer region, comprising epitaxial silicon, having an outer surface adjacent the side wall of the trench, an inner surface, a first end, and a second end, wherein the signal transfer region is doped to an impurity concentration to operate in a fully depleted mode,

(ii) a first diffusion region, interior of the side wall of the trench, coupling the first end of the signal transfer region to the second electrode of the signal storage node;

(iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor,

(iv) a gate insulator coating the inner surface of the signal transfer region, and

(v) a gate conductor coating the gate insulator and coupled to the word line,

wherein the signal transfer device has a width around the circumference of the side wall of the trench and a length from the first diffusion region to the second diffusion region and a ratio of width to length greater than 2;

1;

a conductive coupling member coupling a portion of the outer surface of the signal transfer region to a reference potential and to a signal transfer region of at least one other memory device in the array of memory devices;

an annular collar oxide having an outer surface adjacent the side wall of the trench, an inner surface adjacent an upper portion of the second electrode, a first end adjacent an end of the node dielectric, and a second end adjacent the first end of the signal transfer region,

wherein the second electrode and the signal transfer region merge in a merged region, and the first diffusion region is formed in the merged region; and

an oxide isolation region formed adjacent the outer surface of the signal transfer region exclusive of the portion of the outer surface coupled to the conductive coupling member.

13. A memory device comprising:

a bit line conductor;

a word line conductor;

a p-type silicon substrate having a trench with side walls formed in the substrate;

a signal storage node having an n+ polysilicon first electrode, an n+ polysilicon second electrode formed within the trench, and an oxide node dielectric formed between the first and second electrodes; and

a signal transfer device comprising;

(i) an annular p-type epitaxial silicon signal transfer region having an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end,

(ii) an n+ first diffusion region coupling the first end of the signal transfer region to the second electrode of the signal storage node,

(iii) an n+ second diffusion region coupling the second end of the signal transfer region to the bit line conductor,

(iv) an oxide gate insulator coating the inner surface of the signal transfer region,

(v) a gate conductor coating the gate insulator and coupled to the word line conductor; and

a conductive coupling member coupling a portion of the outer surface of the signal transfer region to a reference potential.