Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature

• US 6,144,060 A
• Filed: 07/31/1998
• Issued: 11/07/2000
• Est. Priority Date: 07/31/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-min, Kim, Byung-hee, Kim, Yeong-kwan, Lee, Sang-in, Park, Chang-soo, Park, In-seon
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/127,353
• Time in Patent Office: 830 Days
• Field of Search: 257/296, 257/298, 257/303, 257/306, 257/310, 257/532
• US Class Current: 257/310
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

Integrated circuit devices include a first dielectric layer, an electrically insulating layer on the first dielectric layer and an an aluminum oxide buffer layer formed by atomic layer deposition (ALD) and stabilized by heat treatment at a temperature of less than about 600° C., between the first dielectric layer and the electrically insulating layer. The first dielectric layer may comprise a high dielectric material such as a ferroelectric or paraelectric material. The electrically insulating layer may also comprise a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). To provide a preferred integrated circuit capacitor, a substrate may be provided and an interlayer dielectric layer may be provided on the substrate. Here, a metal layer may also be provided between the interlayer dielectric layer and the first dielectric layer. The metal layer may comprise a material selected from the group consisting of Pt, Ru, Ir, and Pd.

Claims

1. An integrated circuit capacitor, comprising:

a first capacitor electrode;

a first high dielectric layer on said first capacitor electrode;

a second capacitor electrode on said first high dielectric layer, opposite said first capacitor electrode;

an electrically insulating layer on said first high dielectric layer; and

an aluminum oxide buffer layer formed by atomic layer deposition and stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C., extending between said first high dielectric layer and said electrically insulating layer.

2. The capacitor of claim 1, wherein said first high dielectric layer comprises a material selected from the group consisting of PZT, BaTiO₃, PbTiO₃, STO and BST.

3. The capacitor of claim 1, wherein said electrically insulating layer comprises a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG).

4. The capacitor of claim 1, further comprising:

a substrate;

an interlayer insulating layer on said substrate; and

a metal layer disposed between said interlayer insulating layer and said first high dielectric layer.

5. The capacitor of claim 4, wherein said metal layer comprises a material selected from the group consisting of Pt, Ru, Ir, and Pd.

6. An integrated circuit capacitor, comprising:

a first electrically insulating layer;

a first metal layer pattern on said first electrically insulating layer;

a first high dielectric layer on said first metal layer pattern, opposite said first electrically insulating layer;

a second metal layer pattern on said first high dielectric layer, opposite said first metal layer pattern;

an aluminum oxide buffer layer formed by atomic layer deposition and stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C., on exposed surfaces of said first metal layer pattern, said first high dielectric layer and said second metal layer pattern; and

a second electrically insulating layer on said buffer layer.

7. The capacitor of claim 6, wherein said aluminum oxide buffer layer has a thickness in a range between about 40 Å

and 300 Å

.

8. The capacitor of claim 6, further comprising a barrier layer between said first electrically insulating layer and said first metal layer pattern, said barrier layer comprising aluminum oxide.

9. The capacitor of claim 8, wherein said barrier layer also comprises a metal selected from the group consisting of TiN, TiSiN, TaN, TaSiN, TiAIN, TaAIN and RuO₂.

10. An integrated circuit capacitor, comprising:

a semiconductor substrate;

a first capacitor electrode on said semiconductor substrate and electrically connected thereto;

a capacitor dielectric layer on said first capacitor electrode;

a second capacitor electrode on said capacitor dielectric layer, opposite said first capacitor electrode;

an aluminum oxide layer formed by atomic layer deposition on said second capacitor electrode, said aluminum oxide layer stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C.; and

a first conductive layer pattern formed on said aluminum oxide layer.

11. An integrated circuit capacitor, comprising:

a semiconductor substrate;

a first capacitor electrode on said semiconductor substrate and electrically connected thereto;

a capacitor dielectric layer on said first capacitor electrode;

a second capacitor electrode on said capacitor dielectric layer, opposite said first capacitor electrode;

an aluminum oxide buffer layer formed by atomic layer deposition on said second capacitor electrode, said aluminum oxide buffer layer stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C.; and

a first conductive layer pattern formed on said aluminum oxide buffer layer.

12. The capacitor of 11, wherein said aluminum oxide buffer layer has a thickness in a range between about 10 and 250 Å

.

13. The capacitor of 11, wherein said aluminum oxide buffer layer is formed by atomic layer deposition at a temperature in a range between about 250 and 450°

C.

14. An integrated circuit capacitor, comprising:

a first electrically insulating layer;

a first metal layer pattern on said first electrically insulating layer;

a first high dielectric layer on exposed surfaces of said first metal layer pattern and on said first electrically insulating layer, said first high dielectric layer being patterned in cell block units;

a second metal layer on said first high dielectric layer, opposite said first metal layer pattern, said second metal layer being patterned in cell block units simultaneously with said first high dielectric layer;

an aluminum oxide buffer layer formed by atomic layer deposition and stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C., on said second metal layer; and

a second electrically insulating layer on said buffer layer.

15. The capacitor of claim 14, further comprising:

a contact plug formed in said first electrically insulating layer; and

a barrier layer between said contact plug and said first metal layer pattern.

16. An integrated circuit capacitor, comprising:

lower and upper capacitor electrodes;

a capacitor dielectric layer extending between said lower and upper capacitor electrodes;

an aluminum oxide buffer layer on an upper surface of said upper capacitor electrode, said aluminum oxide buffer layer formed by atomic layer deposition and stabilized by heat treatment at a temperature in a range between about 350°

C. and 600°

C.

17. The capacitor of claim 16, wherein said aluminum oxide buffer layer is stabilized by heat treatment in an oxygen ambient.