Semiconductor device and method of manufacturing the same

• US 6,144,079 A
• Filed: 10/03/1996
• Issued: 11/07/2000
• Est. Priority Date: 04/01/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Okumura, Yoshinori, Shirahata, Masayoshi
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US08/725,386
• Time in Patent Office: 1,496 Days
• Field of Search: 257/392-395, 257/296-300, 438/276, 438/130, 438/526, 438/290
• US Class Current: 257/392
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence

Abstract

In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

Claims

1. A semiconductor device, wherein first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, and concentration profiles of one identical conductivity type impurity in sections extending through channel regions of said first and second MIS transistors in a depth direction from said main surface of said semiconductor substrate have peaks at different depths, wherein

said first MIS transistor has a first channel region provided with a first impurity layer under said first channel region, and said second MIS transistor has a second channel region provided with a second impurity layer having the same conductivity type as said first impurity layer under said second channel region;

and

said second MIS transistor has a higher threshold voltage than said first MIS transistor, and said first impurity layer is formed at a position deeper from said main surface than said second impurity layer.

2. The semiconductor device according to claim 1, wherein impurity concentration distributions of said first and second impurity layers are different from each other and depend on thresholds of said first and second MIS transistors.

3. The semiconductor device according to claim 1, wherein at least one of impurity concentration profiles in sections extending in a depth direction from said main surface through said first and second channel regions has two or more peak values.

4. The semiconductor device according to claim 1, wherein said first and second impurity layers have different kinds of impurity.

5. The semiconductor device according to claim 1, wherein

a third MIS transistor of the conductivity type same as that of said first and second MIS transistors is further formed at a main surface of a semiconductor substrate;

said first, second and third MIS transistors form a sense amplifier, a peripheral circuit and a memory cell, respectively; and

impurity concentration profiles in sections extending in a depth direction from said main surface through channel regions of said first, second and third MIS transistors have peaks at different depths, respectively.

6. The semiconductor device according to claim 1, wherein;

said first and second MIS transistors have first and second channel regions, respectively;

a first heavily doped layer is provided at a predetermined depth from said main surface under said first channel region;

a second heavily doped layer is provided at the substantially same depth as said first heavily doped layer from said main surface under said second channel region; and

an impurity layer between said second heavily doped layer and said main surface under said second channel region.

7. The semiconductor device according to claim 6, wherein

said impurity layer formed under said second channel region has a plurality of layers formed at different depths between said second heavily doped layer and said main surface.

8. The semiconductor device according to claim 6, wherein

an impurity contained in said first and second heavily doped layers is different from an impurity contained in said impurity layer.