Semiconductor integrated circuit having a logic verifying structure and method of manufacturing the same
First Claim
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1. A semiconductor integrated circuit having a logic verification structure, comprising:
- a logic circuit formed of a CMOS structure on a semiconductor substrate of a first conductive type; and
, an impurity region formed on the semiconductor substrate, the impurity region being of a second conductive type opposite to the first conductive type to provide only one pn junction between the impurity region and a back surface of the semiconductor substrate, wherein the impurity region is connected with an output wiring of the logic circuit but independent from the logic circuit, wherein the pn junction is irradiated by a laser beam from the back surface of the semiconductor substrate to generate an electron-hole pair, an electron of which pair is supplied from the impurity region to the output wiring to reveal a logic state of the logic circuit.
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Abstract
A semiconductor integrated circuit having a logic verification structure includes a logic circuit formed by CMOS structure on a semiconductor substrate, in which the semiconductor integrated circuit has an impurity region irradiated by a laser beam from a back of the semiconductor substrate, for testing the logic circuit, achieving a simple logic analysis.
5 Citations
17 Claims
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1. A semiconductor integrated circuit having a logic verification structure, comprising:
- a logic circuit formed of a CMOS structure on a semiconductor substrate of a first conductive type; and
, an impurity region formed on the semiconductor substrate, the impurity region being of a second conductive type opposite to the first conductive type to provide only one pn junction between the impurity region and a back surface of the semiconductor substrate, wherein the impurity region is connected with an output wiring of the logic circuit but independent from the logic circuit, wherein the pn junction is irradiated by a laser beam from the back surface of the semiconductor substrate to generate an electron-hole pair, an electron of which pair is supplied from the impurity region to the output wiring to reveal a logic state of the logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- a logic circuit formed of a CMOS structure on a semiconductor substrate of a first conductive type; and
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12. A semiconductor integrated circuit having a logic verification structure including a logic circuit formed of a CMOS structure on a semiconductor substrate, comprising:
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a semiconductor substrate having a first conductive type; an impurity region formed on the semiconductor substrate, the impurity region having a second conductive type opposite to the first conductive type to provide only one pn junction between the impurity region and a back surface of the semiconductor substrate, wherein the impurity region is electrically connected with an output wiring of the logic circuit but independent from the logic circuit; an insulation film formed on the semiconductor substrate and the impurity region; a contact hole formed on the impurity region by opening the insulation film; a pattern wiring formed on the insulation film and the contact hole; a signal pattern wiring formed above the pattern wiring, a part of which is overlapped with the signal pattern wiring; wherein in the pn junction generates an electron-hole pair upon being irradiated with a laser beam, an electron of which pair is supplied from the impurity region to the output wiring to reveal the logic circuit in logic state. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification