Digital isolation system with ADC offset calibration

• US 6,144,326 A
• Filed: 03/04/1998
• Issued: 11/07/2000
• Est. Priority Date: 04/22/1997
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Krone, Andrew W., Welland, David R., Dupuis, Timothy J., Sooch, Navdeep S.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US09/034,456
• Time in Patent Office: 979 Days
• Field of Search: 375/257, 375/258, 341/118, 341/120, 341/143, 341/139, 377/33, 374/412, 374/93.28, 374/379
• US Class Current: 341/118
• CPC Class Codes: H03M 3/384 Offset correction removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04M 1/573 Line monitoring circuits for detecting caller identification
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations
• CPC Class Codes: H04M 19/02 providing ringing current or supervisory tones, e.g. dialling tone or busy tone

Abstract

A digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the ADC offset signal during normal operation of the isolation barrier system. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Claims

1. An analog-to-digital converter (ADC) offset calibration system in a digital isolation system having a powered circuit on a first side of a isolation barrier and an isolated circuit on a second side of the barrier, wherein digital signals are transmitted across the isolation barrier, and wherein an ADC requiring calibration is located on the second side of the isolation barrier, the ADC offset calibration system comprising:

a digital integrator connected to receive an output signal from the ADC and to provide an integrated offset calibration signal;

a data register connected to receive and hold the integrated offset calibration signal, the data register outputting a held offset calibration signal;

a digital to analog converter having an input connected to receive the held offset calibration signal and having an output providing an analog offset calibration signal;

wherein the analog offset calibration signal is connected to an input of the ADC requiring calibration.

2. The calibration system of claim 1, further comprising a fixed ADC bias source connected to an input of the ADC to provide a fixed ADC bias level to a signal passing through the ADC.

3. The calibration system of claim 2, further comprising a negative fixed ADC bias source connected to an output of the ADC for removing the fixed ADC bias level from the signal passing through the ADC.

4. The calibration system of claim 1, wherein the digital to analog converter comprises a delta sigma modulator coupled to a one-bit digital to analog converter.

5. The calibration system of claim 4, wherein the delta sigma modulator is located on the first side of the isolation barrier and the one-bit digital to analog converter is located on the second side of the isolation barrier.

6. The calibration system of claim 1, wherein the ADC is located on the second side of the isolation barrier and the integrator is located on the first side of the isolation barrier.

7. The calibration system of claim 1, further comprising a fixed DAC bias source connected to combine a fixed DAC bias signal with the output of the digital integrator, and wherein the data register is connected to receive and hold the combination of the integrated offset calibration signal and the fixed DAC bias signal.

8. The system of claim 7, further comprising a negative fixed DAC bias source connected to an output of the digital to analog converter for removing the fixed DAC bias signal from an output signal from the digital to analog converter.

9. The system of claim 1, wherein the ADC is a delta-sigma ADC and the isolation barrier is a capacitive isolation barrier.

10. A method of performing analog-to-digital converter (ADC) offset calibration in a digital isolation system, comprising:

maintaining a data input signal into an ADC being calibrated at a level of zero;

integrating an output signal from the ADC being calibrated to provide an integrated offset calibration signal;

holding the integrated offset calibration signal in a data register;

converting the integrated offset calibration signal from a digital signal to an analog offset calibration signal;

adding the analog offset calibration signal to said data input signal; and

latching the integrated offset calibration signal in the data register when the output signal from the ADC becomes zero.

11. The method of claim 10, further comprising adding a fixed ADC bias signal to said data input signal before it enters the ADC, and removing the fixed ADC bias signal from the ADC output signal.

12. The method of claim 10, wherein the converting step is performed by a digital-to-analog converter (DAC) that provides a DAC analog output signal, and further comprising adding a fixed DAC bias signal to said integrated offset calibration signal, and storing the resulting signal in the data register;

and removing the fixed DAC bias signal from the DAC analog output signal in order to generate the analog offset calibration signal.

13. The method of claim 12, further comprising forcing an input data signal to the DAC to zero during performance of the calibration method.

14. The method of claim 10, wherein the ADC output signal is transmitted across a capacitive isolation barrier before it is integrated.

15. The method of claim 10, wherein the integrated offset calibration signal is transmitted across a capacitive isolation barrier before it is converted to an analog offset calibration signal.

16. The method of claim 14, wherein the integrated offset calibration signal is transmitted across a capacitive isolation barrier before it is converted to an analog offset calibration signal.

17. The method of claim 10, further comprising subtracting a selected fixed ADC bias signal from the ADC output signal before integrating the output signal.

18. The method of claim 10, further comprising adding a selected fixed DAC bias signal to the integrated offset calibration signal.

19. The method of claim 10, further comprising converting the integrated offset calibration signal from a multi-bit signal to a one-bit digital signal.

20. The method of claim 10, wherein the integrated offset calibration signal is converted from a multi-bit digital signal to a one-bit digital signal using a delta-sigma modulator.