Semiconductor memory device

• US 6,144,616 A
• Filed: 10/29/1999
• Issued: 11/07/2000
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Kotoku, Suzuki, Takaaki
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/429,472
• Time in Patent Office: 375 Days
• Field of Search: 365/189.01, 365/230.01, 365/230.06, 365/230.08, 365/189.05, 365/189.07
• US Class Current: 365/233.19
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A semiconductor memory device operating in synchronism with a clock includes an address latch&comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command. A write data buffer part holds a data signal associated with the write command. The data signal held in the write data buffer part is read as a data signal requested by the read command when the first and second address signals coincide with each other.

Claims

1. A semiconductor memory device operating in synchronism with a clock, comprising:

an address latch&

comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command; and

a write data buffer part holding a data signal associated with said write command,

the data signal held in the write data buffer part being read as a data signal requested by said read command when the first and second address signals coincide with each other.

2. The semiconductor memory device as claimed in claim 1, wherein a first interval between the write command and a next read command is the same as a second interval between the write command and a next write command.

3. The semiconductor memory device as claimed in claim 1, wherein a first interval between the write command and a next write command depends on an operation of a sense amplifier provided in the semiconductor memory device.

4. The semiconductor memory device as claimed in claim 1, wherein the address latch&

comparator part continues to hold the address signal associated with said write command until a next write command is received.

5. The semiconductor memory device as claimed in claim 1, wherein the address latch&

comparator part continues to hold the address signal associated with said write command until a read command addressed to a bank different from that addressed by said write command is received.

6. The semiconductor memory device as claimed in claim 1, wherein, when the address latch&

comparator part detects that the first and second address signals coincide with each other, the data signal held in the write data buffer part is read as the data signal requested by said read command.

7. The semiconductor memory device as claimed in claim 1, wherein, when the data signal associated with the write command includes data to be masked, a part of the data signal except for the data to be masked is read from the write data buffer part.

8. The semiconductor memory device as claimed in claim 1, wherein the write command is a page-mode write command and the read command is a page-mode read command.

9. The semiconductor memory device as claimed in claim 1, wherein the address latch&

comparator part continues to hold the address signal associated with said write command which is a page-mode write command until a next page-mode write command or a page-mode close command is received.

10. The semiconductor memory device as claimed in claim 1, further comprising:

a memory cell array;

a sense amplifier; and

bit lines coupled between the memory cell array and the sense amplifier.

11. The semiconductor memory device as claimed in claim 10, wherein the address latch&

comparator part continues to hold the address signal associated with said write command until a next write command is received, and the data signal held in the write data buffer part is read by the address signal held in the address latch&

comparator part.

12. The semiconductor memory device as claimed in claim 10, wherein the address latch&

comparator part continues to hold the address signal associated with said write command until a read command addressed to a bank different from that addressed by said write command is received, and the data signal held in the write data buffer part is read by the address signal held in the address latch&

comparator part.

13. The semiconductor memory device as claimed in claim 10, wherein the address latch&

comparator part continues to hold the address signal associated with said write command which is a page-mode write command until a next page-mode write command or a page-mode close command is received, and the data signal held in the write data buffer part is read by the address signal held in the address latch&

comparator part.

14. The semiconductor memory device as claimed in claim 1, wherein the semiconductor memory device has a write data latency different from a read data latency.

23. The semiconductor memory device as claimed in claim 1, further comprising an interface common to data input and output operations.

24. The semiconductor memory device as claimed in claim 1, further comprising a separate interface separately provided to data input and output operations.

27. The semiconductor memory device as claimed in claim 1, further comprising a plurality of banks, each including the respective, write data buffer part.

15. A semiconductor memory device operating in synchronism with a clock, comprising:

an address latch&

comparator part latching first address signals associated with write commands and comparing the first address signals with a second address signal associated with a read command; and

a write data buffer part holding data signals respectively associated with said write commands,

one of the data signals held in the write data buffer part being read as a data signal requested by said read command when the second address signal coincides with one of the first address signals.

16. The semiconductor memory device as claimed in claim 15, wherein the write commands are page-mode write commands and the read command is a page-mode read command.

17. The semiconductor memory device as claimed in claim 15, wherein a first interval between the write command and a next read command is the same as a second interval between the write command and a next write command.

18. The semiconductor memory device as claimed in claim 15, wherein a first interval between the write command and a next write command depends on an operation of a sense amplifier provided in the semiconductor memory device.

19. The semiconductor memory device as claimed in claim 15, wherein the address latch&

comparator part includes N first parts which latch the first address signals of the respective write commands previously received where N is an integer.

20. The semiconductor memory device as claimed in claim 19, wherein:

the write data buffer part comprises N second parts which hold the data signals associated with the respective write commands; and

one of the data signals respectively held in the N second parts is read as the data signal requested by said read command when the address signal of the read command coincides with one of the address signals held in the N first parts of the address latch&

comparator part.

21. The semiconductor memory device as claimed in claim 15, further comprising:

a memory cell array;

a sense amplifier; and

bit lines coupled between the memory cell array and the sense amplifier.

22. The semiconductor memory device as claimed in claim 15, wherein the data signal associated with an oldest one of the write commands held in the write data buffer part is written into a memory cell array of the semiconductor memory device in accordance with a corresponding one of the first address signals latched in the address latch&

comparator part.

25. The semiconductor memory device as claimed in claim 15, further comprising an interface common to data input and output operations.

26. The semiconductor memory device as claimed in claim 15, further comprising a separate interface separately provided to data input and output operations.

28. The semiconductor memory device as claimed in claim 15, further comprising a plurality of banks, each including the respective, write data buffer part.