Semiconductor memory device
First Claim
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1. A semiconductor memory device operating in synchronism with a clock, comprising:
- an address latch&
comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command; and
a write data buffer part holding a data signal associated with said write command,the data signal held in the write data buffer part being read as a data signal requested by said read command when the first and second address signals coincide with each other.
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Abstract
A semiconductor memory device operating in synchronism with a clock includes an address latch&comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command. A write data buffer part holds a data signal associated with the write command. The data signal held in the write data buffer part is read as a data signal requested by the read command when the first and second address signals coincide with each other.
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Citations
28 Claims
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1. A semiconductor memory device operating in synchronism with a clock, comprising:
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an address latch&
comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command; anda write data buffer part holding a data signal associated with said write command, the data signal held in the write data buffer part being read as a data signal requested by said read command when the first and second address signals coincide with each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 23, 24, 27)
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15. A semiconductor memory device operating in synchronism with a clock, comprising:
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an address latch&
comparator part latching first address signals associated with write commands and comparing the first address signals with a second address signal associated with a read command; anda write data buffer part holding data signals respectively associated with said write commands, one of the data signals held in the write data buffer part being read as a data signal requested by said read command when the second address signal coincides with one of the first address signals. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 25, 26, 28)
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Specification