Equalization techniques to reduce intersymbol interference

• US 6,144,697 A
• Filed: 04/06/1998
• Issued: 11/07/2000
• Est. Priority Date: 02/02/1998
• Status: Expired due to Fees

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Fevrier, Ian J., Fitz, Michael P., Gelfand, Saul B.
• Primary Examiner(s): Tse, Young T.
• Application Number:
  US09/055,682
• Time in Patent Office: 946 Days
• Field of Search: 375/233, 375/346, 375/348, 375/232, 375/234
• US Class Current: 375/233
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03566 between different tapped delay line structures
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03987 Equalisation for sparse channels

Abstract

Equalization techniques are disclosed to reduce intersymbol interference of a received signal. Intersymbol interference is reduced by feedforward filtering and adjusting the input to the feedforward filter with feedback. This approach facilitates the removal of intersymbol interference from sparse signal portions before sparseness is undermined by other equalization procedures. Also, multiplication operations may be reduced and limited multiplier resources more effectively allocated by applying a threshold test to various multiplier coefficients associated with the equalization technique.

Claims

1. A method, comprising:

receiving a signal with intersymbol interference;

filtering a data stream corresponding to the signal with a first filter to reduce intersymbol interference;

slicing a data sequence corresponding to the data stream after said filtering to provide a corresponding stream of symbols, the symbols each being selected from a predetermined symbol set;

successively shifting each of the symbols through a first number of delay elements; and

further reducing the intersymbol interference by adjusting the data stream input into the first filter with feedback from a first plurality of taps of the first delay elements.

2. The method of claim 1, further comprising determining a number of tap coefficients that meet a predetermined threshold and weighting the first taps with the tap coefficients, wherein the first taps are fewer in number than the first delay elements.

3. The method of claim 2, wherein said determining is performed with a processor and said weighting includes allocating each of the first taps to a different one of the first delay elements with a switching unit controlled by said processor.

4. The method of claim 1, further comprising summing the first taps to provide the feedback.

5. The method of claim 1, further comprising:

sending the stream of symbols through a second filter; and

combining an output of the first filter with an output of the second filter to provide the data sequence.

6. The method of claim 5, wherein the second filter includes a second number of delay elements and a second plurality of taps, and further comprising:

establishing a first threshold and a second threshold;

determining a number of first tap coefficients that each meet the first threshold and a number of second tap coefficients that each meet the second threshold; and

correspondingly weighting each of the first taps with the first tap coefficients and the second taps with the second tap coefficients.

7. The method of claim 6, further comprising allocating each of the first taps to a different one of the first delay elements with a switching unit.

8. The method of claim 6, wherein the first and second thresholds are established as a function of a number of filtering coefficients determined for the first filter.

9. The method of claim 1, further comprising:

determining a number of tentative coefficients;

comparing each of the tentative coefficients to a predetermined threshold to select a set of feedback coefficients as a subset of the tentative coefficients;

providing a first number of the feedback coefficients to a corresponding number of input multipliers for the first filter;

providing a second number of the feedback coefficients to correspondingly weight the first taps.

10. An apparatus for processing a data signal with intersymbol interference, comprising:

a first summing junction to provide a first reduction of the intersymbol interference by adjusting the data signal with a feedback signal;

a first feedforward filter responsive to the data signal after the first reduction to provide a second reduction of the intersymbol interference;

a decision operator responsive to the data signal after the first and second reductions to provide a corresponding stream of symbols, the symbols each being selected from a predetermined symbol set; and

a first feedback delay line with a first number of delay elements and a first plurality of weighted taps, said first feedback delay line being responsive to the stream of symbols to successively shift each of the symbols through the first delay elements and provide the feedback signal to said first summing junction as a function of said first weighted taps.

11. The apparatus of claim 10, further comprising a second feedback delay line with a second number of delay elements and a second plurality of weighted taps, said second feedback delay line being configured to successively shift the stream of symbols through said second delay elements, and

wherein an output of said first feedforward filter and said second weighted taps are combined to provide an input to said decision operator.

12. The apparatus of claim 11, further comprising a processor configured to provide:

a first set of tentative feedback coefficients;

a first set of multiplier coefficients selected as a subset of the first set of tentative coefficients by comparing each of the first set of tentative coefficients to a first predetermined threshold;

a second set of tentative coefficients;

a second set of multiplier coefficients selected as a subset of the second set of tentative coefficients by comparing each of the second set of tentative coefficients to a second predetermined threshold;

wherein the first set of multiplier coefficients are provided to correspondingly weight said first weighted taps and the second set of multiplier coefficients are provided to correspondingly weight said second weighted taps.

13. The apparatus of claim 12, wherein said processor is configured to provide a set of feedforward coefficients for said first feedforward filter and determine the first and second thresholds as a function of the feedforward coefficients.

14. The apparatus of claim 10, wherein said first feedforward filter includes a second number of delay elements, a second number of weighted taps each having a corresponding tap multiplier, a multiplicity of summation elements in one-to-one correspondence with said second delay elements, a plurality of input multipliers each corresponding to a different one of said second delay elements, and an adder.

15. The apparatus of claim 14, further comprising a processor configured to provide:

a set of tentative coefficients;

a set of multiplier coefficients selected as a subset of the set of tentative coefficients by comparing each of the set of tentative coefficients to a predetermined threshold;

wherein a first number of the set of multiplier coefficients are provided to correspondingly weight said first weighted taps and a second number of the set of multiplier coefficients are correspondingly provided to said input multipliers.

16. The apparatus of claim 10, wherein said first weighted taps are fewer in number than said first delay elements and further comprising a switching unit to selectively allocate each of the first weighted taps to a different corresponding one of said first delay elements.

17. The apparatus of claim 10, wherein the data signal corresponds to even numbered samples of an input signal, and further comprising a second summing junction, a second feedforward filter, and a second delay line to process odd numbered values of the input signal.

18. A method comprising:

determining a first set of coefficients for an equalizer receiving a signal with intersymbol interference;

comparing each of the first coefficients to a predetermined threshold to select a second set of threshold coefficients, the second coefficients being a subset of the first coefficients; and

equalizing the signal with the equalizer as a function of the second coefficients to reduce the intersymbol interference and minimize multiplication operations for said equalizing.

19. The method of claim 18, further comprising repeating said determining and said comparing to update the second coefficients for a change in response of a channel providing the signal.

20. The method of claim 18, wherein:

the equalizer has a number of delay elements and a number of multipliers;

the first coefficients have a one-to-one correspondence with the delay elements; and

the second coefficients each correspond to a different one of the multipliers and a different one of the delay elements, the different one of the delay elements being determined in accordance with the one-to-one correspondence of the first coefficients selected to provide the second coefficients.

21. The method of claim 18, further comprising:

providing a number of delay elements and a number of multipliers to perform at least a portion of said equalizing;

allocating each of the multipliers to a selected one of the delay elements in accordance with the second coefficients to optimize said equalizing for sparseness of a postcursor portion of the intersymbol interference.

22. The method of claim 21, wherein aid determining, said comparing, and said allocating are performed in accordance with programming of a processor.

23. The method of claim 21, further comprising:

determining a third set of coefficients after a period of time;

comparing each of the third coefficients to the first threshold to provide a fourth set of coefficients, the fourth coefficients being a subset of the third coefficients; and

reallocating the multipliers in accordance with the fourth set of coefficients.

24. The method of claim 23, wherein the equalizer includes a switching unit controlled by a processor to perform said allocating and said reallocating.

25. The method of claim 18, wherein said equalizing includes:

successively shifting a data stream corresponding to the signal through a feedforward filter having a corresponding number of feedforward taps;

successively shifting a stream of decision symbols corresponding to the signal through a first delay line having a first number of delay elements and a first plurality of feedback taps, the first feedback taps each being weighted by one of the second coefficients; and

adjusting data entering the feedforward filter with a sum of the first feedback taps.

26. The method of claim 25, wherein said equalizing includes:

determining a third set of coefficients;

comparing each of the third coefficients to a second threshold to provide a fourth set of coefficients, the fourth coefficients being a subset of the third coefficients;

successively shifting the stream of decision symbols through a second feedback filter having a second number of delay elements and a second number of feedback taps;

weighting the second feedback taps each with a corresponding one of the fourth coefficients; and

adding together the feedforward taps and the second feedback taps to provide an input to a decision operator generating the stream of decision symbols.

27. The method of claim 25, wherein the feedforward filter includes a second delay line with a second number of delay elements each corresponding to one of the feedforward taps, a plurality of input multipliers each providing a product of one of the decision symbols and a corresponding one of the second coefficients, and further comprising:

feeding back each of the products of the multipliers to a different point along the delay line; and

slicing a summation of the feedforward taps to provide the stream of decision symbols.

28. A method of processing a signal with intersymbol interference, comprising:

successively shifting a data stream corresponding to the signal through a feedforward filter to reduce at least a precursor portion of the intersymbol interference;

successively shifting a stream of decision symbols corresponding to the signal through a first delay line to provide feedback, the first delay line having a first number of delay elements and a first plurality of taps; and

adjusting data entering the feedforward filter with a sum of the first taps to reduce a postcursor portion of the intersymbol interference.

29. The method of claim 28, further comprising:

successively shifting the stream of decision symbols through a second delay line for providing feedback, the second delay line having a second number of delay elements and a second number of taps; and

summing together a number of feedforward taps from the feedforward filter and the second taps to provide an input to a decision operator generating the stream of decision symbols.

30. The method of claim 28, further comprising:

determining a first set of coefficients;

comparing each of the first coefficients to a first predetermined threshold to select a second set of coefficients, the second coefficients being a subset of the first coefficients; and

weighting each of the first taps with a corresponding one of the second coefficients.

31. The method of claim 30, wherein the feedforward filter includes a number of feedforward taps, a second number of delay elements each corresponding to one of the feedforward taps and a plurality of input multipliers to introduce feedback between said second delay elements, said input multipliers each providing a product of one of the decision symbols and a corresponding one of the second coefficients.

32. The method of claim 30, further comprising:

determining a third set of coefficients;

comparing each of the third coefficients to a second predetermined threshold to select a fourth set of coefficients, the fourth coefficients being a subset of the third coefficients;

successively shifting the stream of decision symbols through a second delay line having a second number of delay elements and a second plurality of taps; and

weighting each of the second taps with a corresponding one of the fourth coefficients; and

adding together a number of feedforward taps from the feedforward filter and the second taps to provide an input to a decision operator generating the stream of decision symbols.

33. The method of claim 30, wherein the first taps are fewer in number than the first delay elements and further comprising allocating each of the first taps to a different one of the first delay elements with a switching unit.

34. The method of claim 33, wherein a processor performs said determining, said comparing, said weighting, and said allocating;

and further comprising;

repeating said determining, said comparing, said weighting, and said allocating to update weights of the first feedback taps to accommodate changes in response of a channel providing the signal.

35. An apparatus for reducing intersymbol interference of a signal, comprising:

a first filter with a first number of delay elements each having a corresponding one of a first number of weighted taps configured to reduce the intersymbol interference when the signal is fed therethrough;

a decision operator to provide a number of decision symbols from a predetermined symbol alphabet corresponding to the signal received from said first filter; and

a feedback means for further reducing the intersymbol interference with a number feedback coefficients, said feedback coefficients being selected as a subset of a number of tentative coefficients by comparing each of the tentative coefficients to a predetermined threshold;

wherein at least one input to said first delay elements of said first filter is determined as a function of the feedback coefficients.

36. The apparatus of claim 35, wherein said feedback means includes:

a second number of delay elements to successively shift the decision symbols from said decision operator therethrough and a second number of weighted taps allocated to said second delay elements, said second weighted taps being summed together to provide a feedback adjusted input to said first filter; and

a second filter with a third number of delay elements to successively shift the decision symbols from said decision operator therethrough and a third number of weighted taps allocated to said third delay elements, said third weighted taps being summed with an output of said first filter to provide an input to said decision operator.

37. The apparatus of claim 35, wherein each of said first weighted taps is provided by a corresponding one of a number of tap multipliers, and said feedback means includes a plurality of input multipliers fewer in number than said tap multipliers, said input multipliers each being configured to provide a product of a decision symbol from said decision operator and a corresponding one of the feedback coefficients.