High bandwidth-time product continuously variable controlled delay system

• US 6,144,786 A
• Filed: 03/11/1999
• Issued: 11/07/2000
• Est. Priority Date: 03/11/1999
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Chethik, Frank
• Primary Examiner(s): Phan, James
• Application Number:
  US09/266,646
• Time in Patent Office: 607 Days
• Field of Search: 385/15, 385/24, 385/31, 385/39, 385/32, 359/140, 359/127, 359/195
• US Class Current: 385/24
• CPC Class Codes: G02B 6/2861 using fibre optic delay lines and optical elements associated with them, e.g. for use in signal processing, e.g. filtering delay lines in general H03H, H01P9/00; optical computing devices G06E

Abstract

Delay systems that employ switched discrete delay elements and continuously variable controlled delay elements to achieve a continuous (glitchless) delay range. The delay systems incorporate several technologies and subsystems to realize very high bandwidth-time product delay elements to provide for precise and continuous delay control.

Claims

1. A delay system comprising:

a signal splitter for coupling an input signal along upper and lower signal paths;

an upper discretely switched delay element disposed in the upper signal path;

an upper continuously variable controlled delay element coupled to the upper discretely switched delay element;

a lower discretely switched delay element disposed in the lower signal path;

a lower continuously variable controlled delay element coupled to the lower discretely switched delay element;

a delay error detector coupled to outputs of the upper and lower continuously variable controlled delay elements; and

a signal transfer clutch coupled to the delay error detector which outputs a delayed output signal from the system.

2. The system recited in claim 1 further comprising a delay element controller coupled to the upper and lower discretely switched delay elements, the upper and lower continuously variable controlled delay element, the cross-correlating delay error detector and the signal transfer clutch.

3. The system recited in claim 1 wherein the delay error detector comprises a cross-correlating delay error detector.

4. The system recited in claim 1 wherein the continuously variable controlled delay elements each comprise a variable index fiber.

5. The system recited in claim 4 wherein the continuously variable controlled delay elements comprise:

a tunable laser diode;

a modulator for modulating light from the laser diode; and

an optical detector for receiving modulated light transmitted by the optical fiber and outputting a modulated delayed signal.

6. The system recited in claim 1 wherein the discretely switched delay elements comprise an increment switched optical delay element including:

a laser diode;

a modulator for modulating light output by the laser diode;

a plurality of serially coupled delay sections that each comprise an optical switch coupled by way of a section of optical fiber to an optical coupler; and

an optical detector coupled to a last of the delay sections that outputs a modulated delayed signal.

7. The system recited in claim 1 wherein the optical switches comprise single pole, double throw optical switches.

8. The system recited in claim 1 further comprising a fiber amplifier coupled between a last of the delay sections and the optical detector.

9. The system recited in claim 1 wherein the delay error detector comprises a pair of Gilbert cell bandpass multipliers driven in phase quadrature.

10. The system recited in claim 9 wherein the delay error detector comprises:

upper and lower multipliers disposed in upper and lower signal paths for receiving a first signal at first inputs;

a 90°

hybrid for receiving a second signal and for coupling the second signal to second inputs of the multipliers;

upper and lower low pass filters coupled to outputs of the respective multipliers;

upper and lower square law devices coupled to outputs of the respective low pass filters; and

an output summer coupled to outputs of the respective square law devices.

11. The system recited in claim 9 wherein the delay error detector comprises:

an upper cross-correlator for receiving first and second input signals at first and second inputs;

a lower cross-correlator for receiving the first input signals at a first input;

a delay for delaying the second input signal and for coupling the delayed second input signal to a second input of the lower cross-correlator;

a summing amplifier coupled to outputs of the upper and lower correlators; and

a low pass filter coupled to an output of the summing amplifier.