Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication

• US 6,144,980 A
• Filed: 01/28/1998
• Issued: 11/07/2000
• Est. Priority Date: 01/28/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Oberman, Stuart F.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/014,454
• Time in Patent Office: 1,014 Days
• Field of Search: 408/627-632
• US Class Current: 708/627
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/4991 Overflow or underflow
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only
• CPC Class Codes: G06F 7/49963 Rounding to nearest G06F7/49957 takes precedence
• CPC Class Codes: G06F 7/49994 Sign extension
• CPC Class Codes: G06F 7/53 in parallel-parallel fashion, i.e. both operands being entered in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/5338 each bitgroup having two new bits, e.g. 2nd order MBA
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand'"'"'s most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth'"'"'s algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Claims

1. A multiplier capable of performing both signed and unsigned multiplication comprising:

a multiplicand input configured to receive a multiplicand operand, wherein said multiplicand operand is signed or unsigned, wherein said multiplicand operand is in scalar or packed vector format;

a multiplier input configured to receive a multiplier operand, wherein said multiplier operand is signed or unsigned, wherein said multiplier operand is in scalar or packed vector format;

a partial product generator coupled to said multiplicand input, wherein said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand;

a selection logic unit coupled to said partial product generator and said multiplier input, wherein said selection logic unit is configured to select a plurality of partial products from said partial product generator based upon said multiplier operand; and

an adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a final product.

2. The multiplier as recited in claim 1 further comprising a sign-in input configured to receive a sign-in signal indicative of whether said multiplier is to perform signed or unsigned multiplication.

3. The multiplier as recited in claim 2 further comprising a first AND gate coupled to receive said sign-in signal and at least one bit from said multiplicand operand as inputs, wherein said first AND gate is configured to generate an effective sign for said multiplicand operand, and wherein said effective sign for said multiplicand operand is used by said partial product generator to generate said partial products.

4. The multiplier as recited in claim 3, wherein said first AND gate is configured to receive the most significand bit from said multiplicand operand as an input.

5. The multiplier as recited in claim 4 further comprising a second AND gate coupled to receive said sign-in signal and at least one bit from said multiplier operand as inputs, wherein said second AND gate is configured to generate an effective sign for said multiplier operand, and wherein said effective sign for said multiplier operand is used by said selection logic unit together with said multiplier operand to select said plurality of partial products from said partial product generator.

6. The multiplier as recited in claim 5, wherein said second AND gate is configured to receive the most significand bit from said multiplier operand as an input.

7. The multiplier as recited in claim 6, wherein said partial product generator comprises a plurality of inverters coupled to receive said multiplicand operand and said multiplicand operand'"'"'s effective sign, wherein said plurality of inverters are configured to generate an inverted version of said multiplicand operand.

8. The multiplier as recited in claim 7, wherein said partial product generator further comprises shifting logic coupled to said multiplicand operand, wherein said shifting logic is configured to generate a shifted version of said multiplicand value.

9. The multiplier as recited in claim 8, wherein said plurality of partial products comprises said multiplicand, said inverted version of said multiplicand, and said shifted version of said multiplicand.

10. The multiplier as recited in claim 9, wherein said selection logic unit comprises a plurality of multiplexers each configured to select one partial product from said plurality of partial products generated by said partial product generator.

11. The multiplier as recited in claim 10, wherein each of said multiplexers is configured to receive a subset of bits from said multiplier operand and said multiplier operand'"'"'s effective sign as control signals, wherein said control signals control which of said plurality of partial products generated by said partial product generator are selected.

12. The multiplier as recited in claim 11, wherein said adder is a carry-lookahead adder.

13. The multiplier as recited in claim 11, wherein said adder is a carry-propagate adder.

14. The multiplier as recited in claim 11, wherein said adder is a carry-skip adder.

15. The multiplier as recited in claim 11, wherein each of said plurality of partial products has a constant length regardless of whether said multiplicand operand is signed or unsigned.

16. The multiplier as recited in claim 15, wherein each of said plurality of partial products has a constant length regardless of whether said sign-in signal is asserted or unasserted.

17. A multiplier capable of performing both signed and unsigned multiplication comprising:

an effective sign generator configured to receive a sign-in bit and a most significant bit from a multiplicand operand as an inputs, wherein said effective sign generator is configured to output an effective sign bit corresponding to said multiplicand operand;

a partial product generator coupled to receive said multiplicand operand and said effective sign bit, wherein said multiplicand operand is in scalar or packed vector format, wherein said partial product generator is configured to generate a plurality of partial product values using said multiplicand operand and said effective sign bit;

selection logic coupled to said partial product generator, wherein said selection logic is coupled to receive a multiplier operand, wherein said multiplier operand is in scalar or packed vector format, wherein said selection logic is configured to select a number of partial products from said partial product generator based upon said multiplier operand; and

an adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a product.

18. A method for operating a multiplier within a microprocessor comprising:

receiving a multiplier operand, a multiplicand operand, and a sign-in signal as inputs from functional units within the microprocessor, wherein said multiplier operand is in scalar or packed vector format, wherein said multiplicand operand is in scalar or packed vector format;

generating an effective sign bit for said multiplicand operand from said sign-in signal and the most significant bit of said multiplicand operand using an AND gate;

calculating a number of partial products from said effective sign bit and said multiplicand operand using inverters and shifting logic;

selecting partial products according to said multiplier operand;

summing the selected partial products; and

outputting the results.

19. The method as recited in claim 18, further comprising calculating the effective sign for said multiplier operand using said sign-in signal and the most significant bit of said multiplier operand, wherein said selecting is performed according to said multiplier operand'"'"'s effective sign bit and said multiplier operand.

20. The method as recited in claim 19 wherein said calculating and said selecting are performed according to Booth'"'"'s algorithm.