Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication
First Claim
1. A multiplier capable of performing both signed and unsigned multiplication comprising:
- a multiplicand input configured to receive a multiplicand operand, wherein said multiplicand operand is signed or unsigned, wherein said multiplicand operand is in scalar or packed vector format;
a multiplier input configured to receive a multiplier operand, wherein said multiplier operand is signed or unsigned, wherein said multiplier operand is in scalar or packed vector format;
a partial product generator coupled to said multiplicand input, wherein said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand;
a selection logic unit coupled to said partial product generator and said multiplier input, wherein said selection logic unit is configured to select a plurality of partial products from said partial product generator based upon said multiplier operand; and
an adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a final product.
1 Assignment
0 Petitions
Accused Products
Abstract
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand'"'"'s most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth'"'"'s algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
-
Citations
20 Claims
-
1. A multiplier capable of performing both signed and unsigned multiplication comprising:
-
a multiplicand input configured to receive a multiplicand operand, wherein said multiplicand operand is signed or unsigned, wherein said multiplicand operand is in scalar or packed vector format; a multiplier input configured to receive a multiplier operand, wherein said multiplier operand is signed or unsigned, wherein said multiplier operand is in scalar or packed vector format; a partial product generator coupled to said multiplicand input, wherein said partial product generator is configured to generate a plurality of partial products based upon said multiplicand operand; a selection logic unit coupled to said partial product generator and said multiplier input, wherein said selection logic unit is configured to select a plurality of partial products from said partial product generator based upon said multiplier operand; and an adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a final product. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A multiplier capable of performing both signed and unsigned multiplication comprising:
-
an effective sign generator configured to receive a sign-in bit and a most significant bit from a multiplicand operand as an inputs, wherein said effective sign generator is configured to output an effective sign bit corresponding to said multiplicand operand; a partial product generator coupled to receive said multiplicand operand and said effective sign bit, wherein said multiplicand operand is in scalar or packed vector format, wherein said partial product generator is configured to generate a plurality of partial product values using said multiplicand operand and said effective sign bit; selection logic coupled to said partial product generator, wherein said selection logic is coupled to receive a multiplier operand, wherein said multiplier operand is in scalar or packed vector format, wherein said selection logic is configured to select a number of partial products from said partial product generator based upon said multiplier operand; and an adder coupled to said selection logic unit, wherein said adder is configured to sum the partial products selected by said selection unit to form a product.
-
-
18. A method for operating a multiplier within a microprocessor comprising:
-
receiving a multiplier operand, a multiplicand operand, and a sign-in signal as inputs from functional units within the microprocessor, wherein said multiplier operand is in scalar or packed vector format, wherein said multiplicand operand is in scalar or packed vector format; generating an effective sign bit for said multiplicand operand from said sign-in signal and the most significant bit of said multiplicand operand using an AND gate; calculating a number of partial products from said effective sign bit and said multiplicand operand using inverters and shifting logic; selecting partial products according to said multiplier operand; summing the selected partial products; and outputting the results. - View Dependent Claims (19, 20)
-
Specification