Boolean and movement accelerator
First Claim
Patent Images
1. An accelerator circuit comprising:
- boolean unit to perform a boolean operation on first and second data words to output a result word; and
buffer coupled to the boolean unit and having capacity to store at least one block of data, each block being a plurality of words,the circuit being configured to store the first word in the buffer, perform the boolean operation on said first and second words, and store the result word in the buffer overwriting the first word, and further configured to store a first block in the buffer before the boolean unit receives a second block one word at a time.
1 Assignment
0 Petitions
Accused Products
Abstract
An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.
8 Citations
33 Claims
-
1. An accelerator circuit comprising:
-
boolean unit to perform a boolean operation on first and second data words to output a result word; and buffer coupled to the boolean unit and having capacity to store at least one block of data, each block being a plurality of words, the circuit being configured to store the first word in the buffer, perform the boolean operation on said first and second words, and store the result word in the buffer overwriting the first word, and further configured to store a first block in the buffer before the boolean unit receives a second block one word at a time. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A data processor comprising:
-
internal bus; accelerator circuit coupled to the internal bus, the accelerator circuit having bus interface coupled to the internal bus; boolean unit to perform a boolean operation on first and second data words received from the bus interface to output a result word; and buffer coupled to the boolean unit and having capacity to store at least one block of data, each block being a plurality of words, the accelerator circuit to store the first word in the buffer, perform the boolean operation on said first and second words, store the result word in the buffer overwriting the first word, and transfer the result word to the bus interface, and further configured to store a first block in the buffer before the boolean unit receives a second block one word at a time. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
-
-
15. A computer system comprising:
-
local memory; data processor having an internal bus, the local memory being coupled to the internal bus; and application accelerator unit (AAU) integrated in the data processor and coupled to the internal bus, the AAU having a boolean unit to perform a boolean operation on first and second data words to output a result word and a buffer coupled to the boolean unit and having capacity to store a block of data being a plurality of words, the AAU to fetch the first word and the second word from the local memory and store the first word in the buffer, perform the boolean operation on said first and second words, and store the result word in the buffer overwriting the first word, the AAU being further configured to store a first block in the buffer before the boolean unit receives a second block one word at a time. - View Dependent Claims (16, 17, 18, 19, 20, 21)
-
-
22. A method comprising:
-
a) storing a first block of data in a buffer, the first block being a plurality of data words including a first word; and
thenb) performing a boolean operation between the first word in the buffer and a first corresponding word of a second block being received one word at a time and not stored in the buffer, to yield a first result word; c) storing the first result word in the buffer overwriting the first word; d) repeating steps b) and c) upon a second word in the buffer and a second corresponding word of the second block not stored in the buffer, to yield a second result word, the second result word being stored in the buffer overwriting the second word; and e) transferring the first and second result words to a memory. - View Dependent Claims (23, 24)
-
-
25. A data processor comprising:
-
an internal bus; an accelerator circuit coupled to the internal bus, the accelerator circuit having a bus interface coupled to the internal bus, a boolean unit to perform a boolean operation on first and second data words received from the bus interface to output a result word, a buffer coupled to the boolean unit and having capacity to store at least one block of data, each block being a plurality of words, the accelerator circuit being configured to store the first word in the buffer, perform the boolean operation on said first and second words, store the result word in the buffer overriding the first word, and transfer the result word to the bus interface; and a plurality of memory-mapped address registers being a programming interface to the accelerator circuit for programming the addresses of the first and second words and the result word. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
-
Specification