Data flow integrated circuit architecture

• US 6,145,073 A
• Filed: 10/16/1998
• Issued: 11/07/2000
• Est. Priority Date: 10/16/1998
• Status: Expired due to Term

• Current Assignee: Geo Semiconductor Incorporated
• Original Assignee: Quintessence Architectures, Inc.
• Inventors: Cismas, Sorin C.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/174,439
• Time in Patent Office: 753 Days
• Field of Search: 712/25, 712/34, 712/33, 712/29, 712/27, 712/26, 712/200, 712/1, 709/400
• US Class Current: 712/25
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Pre-designed and verified data-driven hardware cores (intellectual property, functional blocks) are assembled to generate large systems on a single chip. Token transfer between cores is achieved upon synchronous assertion, over dedicated connections, of a one-bit ready signal by the transmitter and a one-bit request signal by the receiver. The ready-request signal handshake is necessary and sufficient for token transfer. There are no combinational paths through the cores, and no latches or master controller are used. The architecture and interface allow a significant simplification in the design and verification of large systems integrated on a single chip.

Claims

1. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:

a) a first input interface connected to said second core, comprising

a first input request connection for asserting a first input request signal to said second core,

a first input ready connection for receiving a first input ready signal asserted by said second core, and

a first input data connection for receiving a first input token from said second core;

b) data processing logic connected to said first input data connection, for generating a first output token from said first input token;

c) a first output interface connected to said data processing logic and said third core, comprising

a first output request connection for receiving a first output request signal asserted by said third core,

a first output ready connection for asserting a first output ready signal to said third core, and

a first output data connection connected to said data processing logic, for transmitting said first output token to said third core;

d) first input control logic connected to said first input interface, for controlling said first core to receive said first input token if said first input request signal and said first input ready signal are asserted with a predetermined synchronous relationship; and

e) first output control logic connected to said first output interface, for controlling said first core to transmit said first output token to said third core if said first output request signal and said first output ready signal are asserted with a predetermined synchronous relationship.

2. The system of claim 1 wherein:

a) said first input control logic comprises logic for controlling said first core to receive said first input token if said first input request signal and said first input ready signal are asserted synchronously; and

b) said first output control logic comprises logic for controlling said first core to transmit said first output token to said third core if said first output request signal and said first output ready signal are asserted synchronously.

3. The system of claim 2 wherein:

a) said first input control logic comprises logic for controlling said first core to receive said first input token synchronously with said first input request signal and said input ready signal; and

b) said first output control logic comprises logic for controlling said first core to transmit said first output token synchronously with said first output request signal and said output ready signal.

4. The system of claim 1 wherein:

a) said data processing logic comprises logic for generating a second output token from said first input token;

b) said first core further comprises a second output interface connected to said data processing logic and to a fourth core integrated on said chip, said second output interface comprising

a second output request connection for receiving a second output request signal asserted by said fourth core,

a second output ready connection for asserting a second output ready signal to said fourth core, and

a second output data connection connected to said data processing logic, for transmitting said second output token to said fourth core; and

c) said first core further comprises second output control logic connected to said second output interface, for controlling said first core to transmit said second output token to said fourth core if said second output request signal and said second output ready signal are asserted synchronously.

5. The system of claim 1 wherein:

a) said first output interface is further connected to a fourth core integrated on said chip, said first output interface further comprising

a second output request connection for receiving a second output request signal asserted by said fourth core,

a second output ready connection for asserting a second output ready signal to said fourth core; and

b) said first output control logic comprises logic for controlling said first core to transmit said first output token to said fourth core if said second output request signal and said second output ready signal are asserted synchronously.

6. The system of claim 1 wherein:

a) said first core further comprises a second input interface connected to said data processing logic and to a fourth core integrated on said chip, said second input interface comprising

a second input ready connection for receiving a second input ready signal asserted by said fourth core,

a second input request connection for asserting a second input request signal to said fourth core, and

a second input data connection connected to said data processing logic, for receiving a second input token from said fourth core;

b) said first core further comprises second input control logic connected to said second input interface, for controlling said first core to receive said second input token from said fourth core if said second input request signal and said second input ready signal are asserted synchronously; and

c) said data processing logic comprises logic for generating said first output token from said first input token and said second input token.

7. The system of claim 1 wherein said first core comprises a plurality of pipestages including an input interface pipestage comprising at least two register levels for simultaneously holding at least two tokens.

8. The system of claim 1 wherein said first core comprises a plurality of pipestages including an output interface pipestage comprising at least two register levels for simultaneously holding at least two tokens.

9. The system of claim 1 wherein said first core further comprises a random access memory interface connected to said data processing logic and to a random access memory integrated on said chip.

10. A data processing system comprising a first data-driven core and a second data-driven core integrated on a chip, said first core comprising:

a) a first input interface connected to said second core, comprising

a first input request connection for asserting a first input request signal to said second core,

a first input ready connection for receiving a first input ready signal asserted by said second core, and

a first input data connection for receiving a first input token from said second core;

b) data processing logic connected to said first input data connection, for generating a first output token from said first input token; and

c) first control logic connected to said first input interface and responsive to said first input ready signal, for controlling said first core to receive said first input token from said second core synchronously with said first input ready signal and said input request signal.

11. The system of claim 10 wherein:

a) said first core further comprises a second input interface connected to said data processing logic and to a third core integrated on said chip, said second input interface comprising

a second input ready connection for receiving a second input ready signal asserted by said third core,

a second input request connection for asserting a second input request signal to said third core, and

a second input data connection connected to said data processing logic, for receiving a second input token from said third core;

b) said first core further comprises second control logic connected to said second input interface and responsive to said second input ready signal, for controlling said first core to receive said second input token from said third core synchronously with said second input request signal and said second input ready signal; and

c) said data processing logic comprises logic for generating said first output token from said first input token and said second input token.

12. The system of claim 10 wherein said first core comprises a plurality of pipestages including an input interface pipestage comprising at least two register levels for simultaneously holding at least two tokens.

13. A data processing system comprising a first data-driven core and a second data-driven core integrated on a chip, said first core comprising:

a) a first output interface connected to said second core, comprising

a first output ready connection for asserting a first output ready signal to said second core,

a first output request connection for receiving a first output request signal asserted by said second core, and

a first output data connection for sending a first output token to said second core;

b) data processing logic connected to said first output data connection, for generating said first output token from a first input token; and

c) first control logic connected to said first output interface and responsive to said first output request signal, for controlling said first core to transmit said first output token to said second core synchronously with said first output request signal and said first output ready signal.

14. The system of claim 13 wherein:

a) said data processing logic comprises logic for generating a second output token from said first input token;

b) said first core further comprises a second output interface connected to said data processing logic and to a third core integrated on said chip, said second output interface comprising

a second output request connection for receiving a second output request signal asserted by said third core,

a second output ready connection for asserting a second output ready signal to said third core, and

a second output data connection connected to said data processing logic, for transmitting said second output token to said third core; and

c) said first core further comprises second control logic connected to said second output interface, for controlling said first core to transmit said second output token to said third core synchronously with said second output request signal and said second output ready signal.

15. The system of claim 13 wherein:

a) said first output interface is further connected to a third core integrated on said chip, said first output interface further comprising

a second output request connection for receiving a second output request signal asserted by said third core,

a second output ready connection for asserting a second output ready signal to said third core; and

b) said first control logic comprises logic for controlling said first core to transmit said first output token to said third core synchronously with said second output request signal and said second output ready signal.

16. The system of claim 13 wherein said first core comprises a plurality of pipestages including an output interface pipestage comprising at least two register levels for simultaneously holding at least two tokens.

17. A data processing device comprising a plurality of interconnected data-driven cores integrated on a chip, each of said plurality of cores comprising a plurality of interconnected pipestages, each of said plurality of pipestages comprising:

a) a data path having an input data connection for receiving a first input token, an output data connection for transmitting a first output token derived from said first input token, and a set of token registers situated in said data path between said input data connection and said output data connection, for storing data derived from said first input token;

b) a control path having

a control register for holding a control tag indicative of a storage capability and a transmission capability of said set of token registers; and

control logic connected to an output of said control register, said control logic having

an external input ready connection for receiving an input ready signal,

an external input request connection for asserting an input request signal if said control tag indicates that said each of said pipestages is capable of receiving said first input token,

an external output ready connection for asserting an output ready signal if said control tag indicates that said each of said pipestages is capable of transmitting said output token, and

an external output request connection for receiving an output request signal;

wherein

said control logic is connected to said set of token registers, for controlling said each of said pipestages to receive said first input token if said input ready signal and said input request signal are asserted synchronously, and to transmit said output token if said output ready signal and said output request signal are asserted synchronously; and

said control logic is further connected to an input of said control register for updating said control tag when said each of said pipestages receives said first input token and when said each of said pipestages transmits said first output token.

18. The system of claim 17 wherein said control logic comprises logic for controlling said each of said pipestages to receive said first input token synchronously with said input ready signal and said input request signal, and to transmit said first output token synchronously with said output ready signal and said output request signal.

19. The system of claim 17 wherein said data path further comprises combinational data processing logic connected to said set of token registers, for processing said first input token to generate said first output token.

20. The system of claim 17 wherein said plurality of pipestages comprises an input pipestage, said set of token registers of said input pipestage comprising a first token register R0 for storing a token derived from said first input token, and a second token register R1 for storing a token derived from a second input token received over said input data connection.

21. The system of claim 20 wherein:

an input of said second token register R1 is connected to an output of said first token register R0,

an output of said second token register R1 and said output of said first token register R0 are connected to respective inputs of a multiplexer, and

an output of said multiplexer is connected to said output data connection.

22. The system of claim 17 wherein said plurality of pipestages comprises an output pipestage, said set of token registers of said output pipestage comprising a first token register R0 for storing a token derived from said first input token, and a second token register R1 for storing a token derived from a second input token received over said input data connection.

23. The system of claim 22 wherein:

an output of said first token register R0 is connected to said output data connection,

an input of said first token register R0 is connected to an output of a multiplexer, and

an input and an output of said second token register R1 are connected to respective inputs of said multiplexer.

24. The system of claim 22 wherein said output data connection is in communication with at least two of said plurality of cores.

25. The system of claim 23 wherein said control logic further comprises a DONE register for holding a DONE tag indicative of which of said at least two of said plurality of cores have received said first output token.

26. The system of claim 17 wherein said plurality of pipestages comprises an internal pipestage, said control logic of said internal pipestage comprising:

a) input control interface logic having

a plurality of external input ready connections for receiving a plurality of input ready signals IRDY(j), j=0 . . . K-1, K>

0,

a plurality of internal input request connections for receiving a corresponding plurality of input request signals IREQX(j),

a plurality of external input request connections for asserting said plurality of input request signals IREQ(j), and

an internal input ready connection for asserting an input ready signal IRDYX derived from said plurality of input ready signals IRDY(j) from and said plurality of input request signals IREQX(j);

b) internal control logic connected to said control register, said set of token registers, said plurality of internal input request connections, and said internal input ready connection, for asserting said input request signals IREQX(j) and for controlling said internal pipestage to receive said first input token if said input ready signal IRDYX and an input request signal IREQ(j) corresponding to said first input token are asserted synchronously.

27. The system of claim 26 wherein said input interface logic comprises logic for generating said input ready signal IRDYX according to a relation IRDYX=&

(!IREQX(j)|IRDY(j)), j=0 . . . K-1.

28. The system of claim 17 wherein said plurality of pipestages comprises an internal pipestage, said control logic of said internal pipestage comprising:

a) output control interface logic having

a plurality of external output request connections for receiving a plurality of output request signals OREQ(j), j=0 . . . K-1, K>

0,

an internal output ready connection for receiving an output ready signal ORDYX,

a plurality of external output ready connections for asserting a plurality of output ready signals ORDY(j) derived from said output ready signal ORDYX and said plurality of input request signals OREQ(j), and

an internal output request connection for asserting an output request signal OREQX derived from said plurality of output request signals OREQ(j);

b) internal control logic connected to said control register, said set of token registers, said internal output request connection, and said internal input output connection, for asserting said output ready signal ORDYX if said control tag indicates that said internal pipestage is capable of transmitting said first output token, and for controlling said internal pipestage to transmit said first output token if said output request signal OREQX and said output ready signal ORDYX are asserted synchronously.

29. The system of claim 28 wherein said output interface logic comprises logic for generating said output request signal OREQX according to a relation OREQX=&

OREQ(j), j=0 . . . K-1, and for generating said plurality of output ready signals ORDY(j) according to a relation selected from

space="preserve" listing-type="equation">ORDY(j)=ORDYX&

(&

OREQ(j'"'"')),j'"'"'=(0 . . . j-1, j+1 . . . K-1)

and

space="preserve" listing-type="equation">ORDY(j)=ORDYX&

·

(&

OREQ(j'"'"')),j'"'"'=(0 . . . K-1).

30. A method of generating an output token comprising:

a) providing a first data-driven core, a second data-driven core connected to an input of said first core, and a third data-driven core connected to an output of said first core, wherein said first core, second core, and third core are integrated on a chip;

b) asserting a first input request signal from said first core to said second core over a first input request connection;

c) asserting a first input ready signal from said second core to said first core over a first input ready connection,

d) transmitting a first input token from said second core to said first core if said first input request signal and said first input ready signal are asserted synchronously;

e) generating a first output token from said first input token;

f) asserting a first output request signal from said third core to said first core over a first output request connection;

g) asserting a first output ready signal from said first core to said third core over a first output ready connection; and

h) transmitting said first output token from said first core to said third core if said first output request signal and said first output ready signal are asserted synchronously.

31. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:

a) means for asserting a first input request signal from said first core to said second core over a first input request connection;

b) means for asserting a first input ready signal from said second core to said first core over a first input ready connection,

c) means for transmitting a first input token from said second core to said first core if said first input request signal and said first input ready signal are asserted synchronously;

d) means for generating a first output token from said first input token;

e) means for asserting a first output request signal from said third core to said first core over a first output request connection;

f) means asserting a first output ready signal from said first core to said third core over a first output ready connection; and

g) means for transmitting said first output token from said first core to said third core if said first output request signal and said first output ready signal are asserted synchronously.

32. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:

an input interface connected to said second core, comprising

an input request connection for asserting an input request signal to said second core,

an input ready connection for receiving an input ready signal asserted by said second core, and

an input data connection for receiving an input token from said second core if said input request signal and said input ready signal are asserted synchronously;

processing logic connected to said input data connection, for generating an output token from said input token; and

an output interface connected to said processing logic and said third core, comprising

an output request connection for receiving an output request signal asserted by said third core,

an output ready connection for asserting an output ready signal to said third core, and

an output data connection connected to said processing logic, for transmitting said output token to said third core if said output request signal and said output ready signal are asserted synchronously.

33. A method of designing a data processing system, comprising:

a) providing a plurality of core representations encoding a corresponding plurality of data-driven cores, each of said plurality of cores comprising

an input request connection for asserting an input request signal;

an input ready connection for receiving an input ready signal;

a first input data connection for receiving an input token;

input interface control logic connected to said input request connection, said input ready connection, and said input data connection, for controlling said each of said plurality of cores to receive said input token if said input request signal and said input ready signal are asserted synchronously;

data processing logic connected to said input data connection, for generating an output token from said input token;

an output request connection for receiving an output request signal;

an output ready connection for asserting an output ready signal;

an output data connection connected to said data processing logic, for transmitting said output token; and

output interface control logic connected to said output request connection, said output ready connection, and said output data connection, for controlling said each of said plurality of cores to transmit said output token if said output request signal and said output ready signal are asserted synchronously;

b) interconnecting said core representations to generate a representation of said system; and

c) implementing said representation of said system on a single chip.