Data flow integrated circuit architecture
First Claim
1. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:
- a) a first input interface connected to said second core, comprisinga first input request connection for asserting a first input request signal to said second core,a first input ready connection for receiving a first input ready signal asserted by said second core, anda first input data connection for receiving a first input token from said second core;
b) data processing logic connected to said first input data connection, for generating a first output token from said first input token;
c) a first output interface connected to said data processing logic and said third core, comprisinga first output request connection for receiving a first output request signal asserted by said third core,a first output ready connection for asserting a first output ready signal to said third core, anda first output data connection connected to said data processing logic, for transmitting said first output token to said third core;
d) first input control logic connected to said first input interface, for controlling said first core to receive said first input token if said first input request signal and said first input ready signal are asserted with a predetermined synchronous relationship; and
e) first output control logic connected to said first output interface, for controlling said first core to transmit said first output token to said third core if said first output request signal and said first output ready signal are asserted with a predetermined synchronous relationship.
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Accused Products
Abstract
Pre-designed and verified data-driven hardware cores (intellectual property, functional blocks) are assembled to generate large systems on a single chip. Token transfer between cores is achieved upon synchronous assertion, over dedicated connections, of a one-bit ready signal by the transmitter and a one-bit request signal by the receiver. The ready-request signal handshake is necessary and sufficient for token transfer. There are no combinational paths through the cores, and no latches or master controller are used. The architecture and interface allow a significant simplification in the design and verification of large systems integrated on a single chip.
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Citations
33 Claims
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1. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:
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a) a first input interface connected to said second core, comprising a first input request connection for asserting a first input request signal to said second core, a first input ready connection for receiving a first input ready signal asserted by said second core, and a first input data connection for receiving a first input token from said second core; b) data processing logic connected to said first input data connection, for generating a first output token from said first input token; c) a first output interface connected to said data processing logic and said third core, comprising a first output request connection for receiving a first output request signal asserted by said third core, a first output ready connection for asserting a first output ready signal to said third core, and a first output data connection connected to said data processing logic, for transmitting said first output token to said third core; d) first input control logic connected to said first input interface, for controlling said first core to receive said first input token if said first input request signal and said first input ready signal are asserted with a predetermined synchronous relationship; and e) first output control logic connected to said first output interface, for controlling said first core to transmit said first output token to said third core if said first output request signal and said first output ready signal are asserted with a predetermined synchronous relationship. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processing system comprising a first data-driven core and a second data-driven core integrated on a chip, said first core comprising:
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a) a first input interface connected to said second core, comprising a first input request connection for asserting a first input request signal to said second core, a first input ready connection for receiving a first input ready signal asserted by said second core, and a first input data connection for receiving a first input token from said second core; b) data processing logic connected to said first input data connection, for generating a first output token from said first input token; and c) first control logic connected to said first input interface and responsive to said first input ready signal, for controlling said first core to receive said first input token from said second core synchronously with said first input ready signal and said input request signal. - View Dependent Claims (11, 12)
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13. A data processing system comprising a first data-driven core and a second data-driven core integrated on a chip, said first core comprising:
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a) a first output interface connected to said second core, comprising a first output ready connection for asserting a first output ready signal to said second core, a first output request connection for receiving a first output request signal asserted by said second core, and a first output data connection for sending a first output token to said second core; b) data processing logic connected to said first output data connection, for generating said first output token from a first input token; and c) first control logic connected to said first output interface and responsive to said first output request signal, for controlling said first core to transmit said first output token to said second core synchronously with said first output request signal and said first output ready signal. - View Dependent Claims (14, 15, 16)
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17. A data processing device comprising a plurality of interconnected data-driven cores integrated on a chip, each of said plurality of cores comprising a plurality of interconnected pipestages, each of said plurality of pipestages comprising:
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a) a data path having an input data connection for receiving a first input token, an output data connection for transmitting a first output token derived from said first input token, and a set of token registers situated in said data path between said input data connection and said output data connection, for storing data derived from said first input token; b) a control path having a control register for holding a control tag indicative of a storage capability and a transmission capability of said set of token registers; and control logic connected to an output of said control register, said control logic having an external input ready connection for receiving an input ready signal, an external input request connection for asserting an input request signal if said control tag indicates that said each of said pipestages is capable of receiving said first input token, an external output ready connection for asserting an output ready signal if said control tag indicates that said each of said pipestages is capable of transmitting said output token, and an external output request connection for receiving an output request signal;
whereinsaid control logic is connected to said set of token registers, for controlling said each of said pipestages to receive said first input token if said input ready signal and said input request signal are asserted synchronously, and to transmit said output token if said output ready signal and said output request signal are asserted synchronously; and said control logic is further connected to an input of said control register for updating said control tag when said each of said pipestages receives said first input token and when said each of said pipestages transmits said first output token. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method of generating an output token comprising:
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a) providing a first data-driven core, a second data-driven core connected to an input of said first core, and a third data-driven core connected to an output of said first core, wherein said first core, second core, and third core are integrated on a chip; b) asserting a first input request signal from said first core to said second core over a first input request connection; c) asserting a first input ready signal from said second core to said first core over a first input ready connection, d) transmitting a first input token from said second core to said first core if said first input request signal and said first input ready signal are asserted synchronously; e) generating a first output token from said first input token; f) asserting a first output request signal from said third core to said first core over a first output request connection; g) asserting a first output ready signal from said first core to said third core over a first output ready connection; and h) transmitting said first output token from said first core to said third core if said first output request signal and said first output ready signal are asserted synchronously.
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31. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:
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a) means for asserting a first input request signal from said first core to said second core over a first input request connection; b) means for asserting a first input ready signal from said second core to said first core over a first input ready connection, c) means for transmitting a first input token from said second core to said first core if said first input request signal and said first input ready signal are asserted synchronously; d) means for generating a first output token from said first input token; e) means for asserting a first output request signal from said third core to said first core over a first output request connection; f) means asserting a first output ready signal from said first core to said third core over a first output ready connection; and g) means for transmitting said first output token from said first core to said third core if said first output request signal and said first output ready signal are asserted synchronously.
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32. A data processing system comprising a first data-driven core, a second data-driven core, and a third data-driven core integrated on a chip, said first core comprising:
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an input interface connected to said second core, comprising an input request connection for asserting an input request signal to said second core, an input ready connection for receiving an input ready signal asserted by said second core, and an input data connection for receiving an input token from said second core if said input request signal and said input ready signal are asserted synchronously; processing logic connected to said input data connection, for generating an output token from said input token; and an output interface connected to said processing logic and said third core, comprising an output request connection for receiving an output request signal asserted by said third core, an output ready connection for asserting an output ready signal to said third core, and an output data connection connected to said processing logic, for transmitting said output token to said third core if said output request signal and said output ready signal are asserted synchronously.
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33. A method of designing a data processing system, comprising:
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a) providing a plurality of core representations encoding a corresponding plurality of data-driven cores, each of said plurality of cores comprising an input request connection for asserting an input request signal; an input ready connection for receiving an input ready signal; a first input data connection for receiving an input token; input interface control logic connected to said input request connection, said input ready connection, and said input data connection, for controlling said each of said plurality of cores to receive said input token if said input request signal and said input ready signal are asserted synchronously; data processing logic connected to said input data connection, for generating an output token from said input token; an output request connection for receiving an output request signal; an output ready connection for asserting an output ready signal; an output data connection connected to said data processing logic, for transmitting said output token; and output interface control logic connected to said output request connection, said output ready connection, and said output data connection, for controlling said each of said plurality of cores to transmit said output token if said output request signal and said output ready signal are asserted synchronously; b) interconnecting said core representations to generate a representation of said system; and c) implementing said representation of said system on a single chip.
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Specification